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Method for manufacturing a semiconductor device, and semiconductor device

A semiconductor and conductor technology, applied in the field of manufacturing such semiconductor devices, can solve the problems of increased ohmic loss of gate resistance, compromise of device performance, etc.

Active Publication Date: 2016-05-25
INFINEON TECH AUSTRIA AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, reductions in transistor size can lead to compromises in device performance
For example, narrowing of conductive features such as gate electrodes can lead to increased gate resistance, ohmic losses, and / or undesired heating of semiconductor devices, especially when the devices are operated at high current densities

Method used

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  • Method for manufacturing a semiconductor device, and semiconductor device
  • Method for manufacturing a semiconductor device, and semiconductor device
  • Method for manufacturing a semiconductor device, and semiconductor device

Examples

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Embodiment Construction

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustrations specific embodiments in which the invention may be practiced. In this regard, directional terms such as "top", "bottom", "front", "rear", "front", "tail", "transverse", "longitudinal", etc. refer to the (one or more ) orientation of the attached figure to use. Because components of an embodiment may be positioned in many different orientations, directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the scope of the present invention. Accordingly, the following detailed description should not be read in a limiting sense, and the scope of the invention is defined by the appended claims. The described embodiments use specific language, which should not...

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PUM

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Abstract

The invention relates to a method for manufacturing a semiconductor device, and a semiconductor device. The method of manufacturing a semiconductor device includes providing a semiconductor substrate (199) having a main surface (101) and a gate electrode (150) which is within a trench (190) between neighboring semiconductor mesas (191,192). The gate electrode (150) is electrically insulated from the neighboring semiconductor mesas (191,192) by respective dielectric layers. A respective pillar (201,202) on each of the neighboring semiconductor mesas (191,192)is formed, leaving an opening (400) between the pillars (201,202) above the trench (190). Dielectric contact spacers (211,212) are formed in the opening (400) along respective pillar side walls to narrow the opening (400) above the gate electrode (150). A conductor (330) is formed, having an interface (610) with the gate electrode (150). The interface (610) extends along an extension of the gate electrode (150), and the conductor (330) has a conductivity greater than the conductivity of the gate electrode (150).

Description

technical field [0001] Embodiments described herein relate to semiconductor devices including gate electrodes, such as gate electrodes within trenches. Further embodiments relate to methods for fabricating such semiconductor devices. Background technique [0002] It is desirable to design semiconductor devices that can perform reliably under demanding conditions. Semiconductor device performance specifications can be affected by feature size. For example, reductions in transistor size can result in a compromise in device performance. For example, narrowing of conductive features such as gate electrodes can lead to increased gate resistance, ohmic losses, and / or undesired heating of semiconductor devices, particularly when the devices are operated at high current densities. Accordingly, there is a desire to maintain or even improve device performance specifications while allowing miniaturization. Contents of the invention [0003] According to one embodiment, a method f...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/283H01L21/336H01L29/78H01L29/06H01L29/423
CPCH01L21/283H01L29/0603H01L29/401H01L29/4236H01L29/66477H01L29/78H01L21/76897H01L29/407H01L29/41741H01L29/41766H01L29/66348H01L29/66719H01L29/66727H01L29/66734H01L29/7397H01L29/7813H01L2924/0002H01L2924/00H01L21/0337H01L21/28114H01L21/823468H01L29/6656H01L29/7827
Inventor M.珀尔兹尔
Owner INFINEON TECH AUSTRIA AG