Two-step cluster software load feature extraction method based on SOM and K-means

Abstract

The invention discloses a two-step cluster software load feature extraction method based on SOM and K-means. The method comprises the following steps that (1) load features are extracted from a dynamic instruction stream in the software performing process: firstly the software performing process is divided into multiple fragments, then statistics of the feature parameters of each program fragment is performed, and each software outputs multiple sets of feature parameters so as to form a matrix formed by the multi-dimensional feature parameters; (2) typical program fragments are extracted from the feature parameter matrix: feature fragment clusters with different software load features are found from multiple program fragments by utilizing an SOM clustering algorithm, and then the fragment capable of most representing the features of the cluster is found from the feature fragment clusters of the same type by utilizing a K-means clustering algorithm. According to the method, the defects that SOM convergence time is excessively long and the K-means algorithm is excessively sensitive to an initial point and liable to fall into the locally optimal solution can be compensated simultaneously.

Description

technical field [0001] The invention belongs to the field of processor architecture, in particular to a software load feature extraction method based on SOM and K-means two-stage clustering. Background technique [0002] With the advent of the mobile Internet era, our lives are increasingly inseparable from mobile smart terminals. Rich applications require high-performance mobile smart terminal SoC (System on Chip) to provide support to meet user needs. The overall performance of the SoC largely depends on the performance of the microprocessor, that is, the general processing performance of the SoC. With the continuous improvement of SoC performance, the design complexity of the microprocessor is also greatly increased. In order to reduce design costs and design risks, in the chip front-end design stage, designers need to evaluate the architecture design plan, analyze the relevant factors affecting system performance, and determine whether the initial design plan of the sy...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the problems that the software load features in the above-mentioned prior art are many and difficult to extract, t...

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