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A Fast Extraction Method of Expected Stack Distance Based on Statistical Deduction

A technology of stack distance and extraction method, applied in the field of software and hardware co-design, can solve the problem of high time complexity of stack distance extraction algorithm, and achieve the effect of improving prediction speed and ensuring prediction accuracy.

Active Publication Date: 2019-01-04
RES INST OF SOUTHEAST UNIV IN SUZHOU
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Problems solved by technology

[0006] Purpose of the invention: In order to overcome the problem in the prior art that the time complexity of the stack distance extraction algorithm that occurs in the evaluation of LRU-Cache memory access behavior is too high, the present invention provides a method for quickly extracting the expected stack distance based on statistical deduction. On the basis of quickly obtaining the memory access reuse distance, the design formula derives the expected stack distance distribution, which is used to quickly evaluate the LRU-Cache memory access behavior

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  • A Fast Extraction Method of Expected Stack Distance Based on Statistical Deduction
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  • A Fast Extraction Method of Expected Stack Distance Based on Statistical Deduction

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[0035] Below in conjunction with accompanying drawing and specific embodiment, further illustrate the present invention, should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention All modifications of the valence form fall within the scope defined by the appended claims of the present application.

[0036] A fast extraction method of expected stack distance based on statistical deduction, such as Figure 1-3 As shown, firstly, the memory access Trace stream during program execution is obtained through the full-featured simulation model Gem5. And while recording the memory access Trace stream, execute sequence labels for each memory access request; secondly, use the red-black tree data structure to record the address and sequence label of each memory access. The...

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Abstract

The invention discloses a method for rapidly extracting expected stack distance based on statistics and deduction. The method comprises the following steps: acquiring access Trace flow of a target program by way of Gem5, and marking each access request according to an execution order; using the red-black tree index structure to record access addresses and mark; when a reuse occurs, acquiring a reuse distance by subtracting current request execution mark and a previous access mark recorded in the red-black tree. The method of the invention finds out a conversion relationship between the reuse distance and the reuse distance based on a Cache set associative, and derives a conversion relationship between a reuse distance distribution and an expected stack distance. Since the time cost of reuse distance extraction is low, and the expected stack distance distribution based on the Cache set associative can be obtained from the aforementioned two conversion process, the method of the invention substantially increases the velocity of evaluating LRU-Cache access behavior by using the stack distance.

Description

technical field [0001] The invention relates to the field of software-hardware collaborative design, in particular to a method for quickly extracting expected stack distances based on statistical deduction, which is used for evaluating processor Cache memory access performance. Background technique [0002] With the development of semiconductor technology, the computing power of processors has been significantly improved. But the "memory wall" problem seriously affects the computing performance of the processor. As an on-chip cache, Cache can reduce the number of off-chip memory accesses and improve system memory access performance. [0003] In the embedded field, in addition to computing performance, area and power consumption are also important design indicators for system chips. Limited by product launch time and chip design costs, the industry needs to quickly obtain correct hardware design solutions to reduce product design cycles and design costs. Therefore, at the ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0862G06F12/0893
CPCG06F12/0862G06F12/0893
Inventor 季柯丞王芹凌明时龙兴
Owner RES INST OF SOUTHEAST UNIV IN SUZHOU