The internal clock circuit of the sram compiler

Abstract

The invention discloses an internal clock circuit of an SRAM complier.An internal clock generator forms a rising edge of an internal clock input signal under the control of an external clock signal; the internal clock input signal passes a selected preset delay circuit and then is input into a bit line controller which outputs a word line signal to a word line; the SRAM complier selects different preset delay circuits according to the size of a storage array.The rising edge of the word line signal starts to perform discharging when a retroposition line is generated, after discharging of the bit line ends, the bit line controller forms a reset pulse signal, and the reset pulse signal is input into the internal clock generator to form a falling edge of the internal clock input signal.The internal clock circuit can optimize small-capacity GTP time sequence of a small-capacity SRAM, increase the reading and writing speed of the small-capacity SRAM, improve self-adaptive capacity on different PVT conditions and reduce the power consumption waste of the small-capacity SRAM, and meanwhile it can be guaranteed that a large-capacity SRAM maintains enough reading and writing margin.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to an internal clock circuit of an SRAM compiler. Background technique [0002] In the internal clock (GTP) circuit of the existing SRAM compiler (Compiler), the width of the internal clock is related to the internal clock driver, such as figure 1 Shown is the internal clock curve generated by the internal clock circuit of the existing SRAM compiler, where: [0003] The signal GTPIN is generated by an internal clock generator (GTP generator) and is a pulse signal. [0004] The signal GTP is formed by inputting the signal GTPIN to an internal clock driver (GTP drive) and outputting it, and the pulse width of the GTP is the same as that of the GTPIN. The signal GTP is input to the network that needs to use the signal GTP inside the SRAM, and the required GTP pulse signal is output to the internal GTP network through the internal clock driver. [0005] The signal MWL is the word...

AI Technical Summary

Problems solved by technology

[0011] 3. The delay of the GTP falling edge generation circuit, that is, the delay t3

When the proportion of MBL discharge delay is too small, it will lead to excessive reading and writing margin, insufficient reading and writing speed, and waste of power consumption; at the same time, the adaptive ability to different PVT conditions is also reduced

Images