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System and method for rasterizing circuit layout data

A database and computing system technology, applied in electrical digital data processing, circuits, CAD circuit design, etc., can solve problems such as lack of verification

Active Publication Date: 2018-11-06
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, while existing lithographic techniques are generally adequate, they have not proven to be fully compliant in all respects

Method used

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  • System and method for rasterizing circuit layout data
  • System and method for rasterizing circuit layout data
  • System and method for rasterizing circuit layout data

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Embodiment Construction

[0033] The present invention relates generally to integrated circuit device fabrication and, more particularly, to systems and techniques for rasterizing polygons of a circuit layout into a grid of pixels, such as for a direct write lithography process.

[0034] The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, or may include an embodiment in which the first component and the second component are formed Embodiments in which additional parts are formed such that the first part and the second part are not in direc...

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Abstract

A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.

Description

technical field [0001] The present invention relates generally to integrated circuit device fabrication and, more particularly, to systems and techniques for rasterizing polygons of a circuit layout into a grid of pixels, such as for a direct write lithography process. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid development. As ICs evolve, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down has also been accompanied by an increase in the complexity of designing and fabricating devices that include these ICs, and similar developments in device design are required in order to realize these advantages. [...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L21/027G06F17/50
CPCG06F30/39H01L21/0274H01L27/0207G03F7/70291G03F7/70383G03F7/70508H01J2237/31764
Inventor 刘沛怡吴政机陈正宏林钜馥王文娟林世杰
Owner TAIWAN SEMICON MFG CO LTD