Speculative Clock Data Recovery Circuitry for High Speed ​​Data Transmission Receivers

Abstract

The invention relates to a speculation type clock data recovery circuit system for a high-speed data transmission receiver. The speculation type clock data recovery circuit system comprises a loop formed by a sampler, a demultiplexer, a phase discriminator, a digital lowpass filter, a decoder and a phase interpolator. The digital lowpass filter comprises at least one accumulator. The accumulator comprises two adders, a multiplexer and a D trigger. Judgment results as advanced or delayed, which are output by the phase discriminator, are used as input of the accumulator. The two adders of the accumulator output two possible accumulation output values advanced or delayed for the current period. Then according to output values of the phase discriminator for the current period, the multiplexer is controlled to select an accurate accumulator output result, which is input to the D trigger. The speculation type clock data recovery circuit system of the invention, which may be one-stage, two-stage or multi-stage, effectively reduces the delay of a clock data loop and enhances the system stability and also the jitter anti-interference ability.

Description

technical field [0001] The invention belongs to the technical field of high-speed data communication integrated circuits, and in particular relates to a novel speculative clock data recovery circuit, which can be applied to receiver systems for various data transmissions. At the receiver side, there is a problem that the received data is not synchronized with the sampling clock. The clock data recovery system continuously adjusts the sampling clock phase to make the sampling clock sample at the data center point with the highest data signal-to-noise ratio. The present invention can reduce the system loop delay , increase system stability and reduce bit error rate. Background technique [0002] The implementation structure of the clock data recovery circuit includes a phase-locked loop (PLL)-based structure, a delay-line loop (DLL)-based structure, a phase-interpolator (PI)-based structure, an analog-to-digital converter (ADC)-based structure, and an oversampling structure, e...

AI Technical Summary

Problems solved by technology

[0006] The present invention proposes a new type of speculative clock data recovery system aiming at the defect that the all-digital clock data recovery circuit is used for the performance degradation of high-speed data communication

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