Optimized phase change memory architecture

Abstract

The invention discloses an optimized phase change memory architecture. Each PCM line consists of a data field and a check field, wherein the check field comprises a grouping information field and an ECC check code field; the data field is stored by adopting a single-layer PCM unit; and the data check field is stored by adopting a double-layer PCM unit. According to the optimized phase change memory architecture, a dynamic grouping manner is adopted, and the data field is dynamically divided into N groups according to the positions of vulnerable bits, so that the vulnerable bits are uniformly distributed in each group and each group at most comprises one vulnerable bit; and meanwhile, grouped ECC check is used, and the double-layer PCM unit is used for storing check bits, so that the length of the check field is increased, the PCM line data error correction ability is improved, more bit errors can be corrected, and the reading voltage can be improved and the reading delay can be decreased while the fault-tolerant ability is strengthened so as to greatly improve the reading speed of the PCM.

Description

technical field [0001] The invention belongs to the technical field of computer storage, and in particular relates to an optimized phase-change memory architecture. Background technique [0002] Phase Change Memory (PCM for short) is a storage technology that develops very rapidly and is very likely to replace the main memory system in the future. It supports high-density, large-scale data storage and is non-volatile. However, phase change memory has a disadvantage, that is, the read and write delay of the current storage device is relatively high, and the write delay is even worse. The basic unit of a phase change memory is composed of a compound sheet of Ge, Sb and Te plus two electrodes. There is a huge difference in the conductivity of the compound in the crystalline state and the amorphous state, and the phase change memory takes advantage of this difference. to store data. Single-layer PCM bits are divided into two states: crystalline state and amorphous state, corr...

AI Technical Summary

Problems solved by technology

However, due to the fact that the physical characteristics of each PCM bit are not exactly the same, under high voltage conditions, a small number of bits will write data by mistake (this phenomenon is called read disturbance)

Since the ECC check can only correct one bit error, in order to avoid multiple read interference error bits in a row, the read voltage cannot be fully increased, so the ideal read speed cannot be achieved

In order to solve the problem of read interference accumulation, someone proposed the PRS (Probabilistic Row Scrubbing) strategy. This strategy performs data verification on frequently accessed data rows according to a certain probability, but it cannot completely solve the problem of read interference accumulation.

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