High Speed ​​Low Power Flip-Flops

Abstract

The invention discloses a high-speed and low-power-consumption flip-flop, comprising a control signal generating circuit, an enabling unit and a latch structure. The latch structure includes two input ends, two output ends, two enabling ends, a second An enabling terminal and a ground terminal, the enabling unit includes two enabling circuits, the output signal X of the control signal generation circuit and the external control signal D are used as the input signals of the first enabling circuit, the first enabling circuit The output terminal of the control signal is connected to the first enable terminal, the output signal X of the control signal generation circuit and the inverted signal DB of the external control signal D are used as the input signal of the second enable circuit, and the output of the second enable circuit Compared with the traditional structure, the flip-flop structure proposed by the present invention has a simple circuit structure, and the parasitic capacitance of the output terminal of the latch is very small, which improves the speed of the flip-flop and has no static power. consumption.

Description

technical field [0001] The invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed and low-power consumption trigger. Background technique [0002] As an important sequential circuit structure, flip-flop is widely used in digital, analog and analog-digital hybrid integrated circuits. In recent years, with the continuous development of integrated circuit manufacturing technology, the demand for high-speed low-power flip-flops has gradually increased. In order to meet the requirements of low power consumption, the power supply voltage has been further reduced. In response to this trend, in order to ensure the working performance of flip-flops , developed some high-speed low-power flip-flop structures, including SAFF (sense amplifier based flip-flop) structure, MSAFF (modified sense amplifier based flip-flop) and SBFF (self-blocking flip-flop) structure, the above three Each structure has its own advantages a...

AI Technical Summary

Problems solved by technology

However, the control signal generation circuit and the enable transistor of the latch are both composed of NMOS transistors connected in series, and the on-resistance is relatively large. At the same time, the parasitic capacitance at the output end of the flip-flop is also relatively large, which is not suitable for high-speed circuit design.

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