Support for ioapic interrupts in amba-based devices

Abstract

A disclosed computing system includes an x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) connected to the PCIe RC by a PCIe link, the PCIe EP being connected to the AMBA bus. The interconnect chip can communicate with the IO devices in an AMBA-compatible manner and with the host system in a PCIe-compatible manner through the AMBA bus. Communication may include receiving a command from the processor, sending the command to the IO device over the AMBA bus, receiving a response from the IO device over the AMBA bus, sending one or more DMA operations to memory over the AMBA bus and PCIe link. Further communication may include sending the IOAPIC interrupt to the host system's processor according to the PCIe ordering rules.

Description

technical field [0001] This application relates to computing systems, and more particularly to support of IOAPIC interrupts in AMBA-based devices. Background technique [0002] Peripheral hardware devices are typically connected to a system on chip (SoC) via a PCIe (Peripheral Component Interconnect Express) interconnect. The SoC and peripheral hardware devices together form a computer. This is the case for a computer running an operating system (OS) configured to run on an x86 processor. The PCIe link allows the attached peripheral hardware device to communicate with the host, specifically to read and write data. Traditionally, x86-based systems have been designed to apply PCIe ordering rules from devices to x86 processors or from x86 processors to devices in an end-to-end manner. Imposing PCIe ordering rules allows correct operation of the producer / consumer communication model prevalent in modern OSes. [0003] The producer-consumer communication model allows both proc...

AI Technical Summary

Problems solved by technology

Due to this incompatibility, AMBA-based peripheral IO devices cannot directly interact with PCIe-based host systems

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