Layout comparing schematic verifying method and device of discrete device

A discrete device and verification method technology, applied in the direction of instruments, electrical digital data processing, special data processing applications, etc., can solve the problems of low efficiency and high error rate of circuit diagrams, and achieve improved efficiency, improved layout accuracy, and rapid batch LVS verification Effect

Active Publication Date: 2016-08-10
SOI MICRO CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The present invention solves the technical problem of low efficiency in drawing circuit diagrams in the prior art for LVS verification of discrete devices by providing a layout comparison schematic verification method and device for discrete devices, and there is no LVS verification without LVS verification. Technical issues with high error rates

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  • Layout comparing schematic verifying method and device of discrete device
  • Layout comparing schematic verifying method and device of discrete device
  • Layout comparing schematic verifying method and device of discrete device

Examples

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Embodiment 1

[0044] In this embodiment, a verification method of layout comparison and schematic diagram of discrete devices is provided, please refer to figure 1 , figure 1 It is a flow chart of the method for verifying the schematic diagram of the layout of the discrete device in the embodiment of the present application, such as figure 1 As shown, the method includes:

[0045] Step S101, marking the ports of the discrete device on the layout of the discrete device;

[0046] Step S102, modifying the layout comparison schematic file, so that when extracting the netlist of the layout of the discrete device, the information of the marked port can be extracted;

[0047] Step S103, receiving a verification operation for triggering verification of the layout comparison schematic diagram;

[0048] Step S104, extracting the netlist of the layout, and comparing the netlist with a pre-stored netlist file to perform layout comparison schematic verification; the netlist file includes the port and...

Embodiment 2

[0102] In this embodiment, a layout comparison schematic verification device for discrete devices is provided, such as Figure 4 As shown, the device includes:

[0103] A marking module 401, configured to mark ports of the discrete device on the layout of the discrete device;

[0104] A modification module 402, configured to modify the layout comparison schematic file, so that when extracting the netlist of the layout of the discrete device, the information of the marked port can be extracted;

[0105] A receiving module 403, configured to receive a verification operation for triggering the verification of the layout comparison schematic diagram;

[0106] The verification module 404 is used to extract the netlist of the layout, and compare the netlist and the pre-stored netlist file, so as to verify the schematic diagram of the layout comparison; the netlist file includes the discrete device to be verified port and process size information.

[0107] In the implementation of...

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Abstract

The invention discloses a layout comparing schematic verifying method and device of a discrete device. The method comprises the following steps: marking ports of the device on a layout of the discrete device; modifying a layout comparing schematic file to ensure that the information of the marked ports can be extracted when a netlist of the layout of the discrete device is extracted; receiving a verifying operation for triggering the layout comparing schematic verifying; and extracting the netlist of the layout and comparing the netlist with a prestored netlist file to carry out the layout comparing schematic verifying, wherein the netlist file comprises port information and process dimension information of the verified device. The method and the device which are provided by the invention have the advantages that the technical problems that in the prior art, circuit drawing is needed for the LVS (Layout Versus Schematics) verification of the discrete device, the efficiency is low and the error rate is high without the LVS verification are solved; and the technical effects of increasing the efficiency of carrying out the LVS verification on the discrete device and increasing the layout accuracy are realized.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a verification method and device for layout comparison and principle diagram of discrete devices. Background technique [0002] In the process of integrated circuit design, in order to ensure the correctness of layout drawing, it is often necessary to perform design verification on the designed layout. Design verification includes DRC (Design Rules Check, design rule verification) and LVS (Layout Versus Schematics, Layout comparison schematic) verification, etc. [0003] As for the PCM (Process Control Monitor, process control monitoring) layout used for process monitoring or the device layout used for parameter extraction, since they are all layouts of discrete devices, if the same LVS verification as integrated circuits is used for such discrete devices method, it is necessary to first draw the circuit diagram of the discrete device according to the design goal, and th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/398
Inventor 卜建辉高立博李多力罗家俊韩郑生
Owner SOI MICRO CO LTD
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