Method and device for realizing flow line of processing instructions and processor

Abstract

The invention provides a method and a device for realizing a flow line of processing instructions and a processor. The flow line of the processing instructions comprises an instruction acquisition stage, a decoding stage and an execution stage. The method comprises the following steps of acquiring a predetermined number of to-be-processed instructions from an instruction memory in the instruction acquisition stage; judging an instruction type of each instruction in the predetermined number of instructions, computing a skip target address when judging that the current instruction is a skip instruction, acquiring a skip target instruction from the instruction memory according to the skip target address and decoding a delay slot instruction after the current instruction and the skip target instruction in the decoding stage; and executing the decoded delay slot instruction and the decoded skip target instruction in sequence in the execution stage. According to the method and the device for realizing the flow line of the processing instructions and the processor, the efficiency of the flow line can be improved; and meanwhile, the hardware cost and the possible delay cost and power consumption cost can be saved.

Description

technical field [0001] The invention relates to the technical field of processor architecture, in particular to a method, device and processor for implementing a pipeline for processing instructions. Background technique [0002] A jump instruction is a processor, such as a MIPS processor, an instruction commonly used in an instruction set architecture, which is used to convert program execution from executing a first sequence of instructions to executing a second sequence of instructions, when the processor fetches a jump instruction from memory , which jumps to the target address and begins execution of the second sequence of instructions. It can be seen that the execution result of the jump instruction directly affects where the subsequent operation obtains the instruction. In addition, the MIPS instruction set stipulates that all jump instructions must have a delay slot instruction. The delay slot instruction is the next instruction immediately after the jump instructio...

AI Technical Summary

Problems solved by technology

[0009] For the first pipeline method of processing instructions, due to the occurrence of "cavitation" in the pipeline, although it can ensure that the processor can correctly fetch instructions, it loses pipeline efficiency;

[0010] For the second pipeline method of processing instructions, since a special branch predictor is required, the hardware overhead is relatively large. In addition, if the jump address prediction is incorrect, additional delay overhead and power consumption overhead will be generated.

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