Packaging structure for photoelectron integrated chip

Abstract

The invention relates to a packaging structure for a photoelectron integrated chip. The packaging structure comprises a dielectric substrate, a metallic conduction post, and a matched resistor. A ground electrode G, a signal electrode S, a matched resistor for impedance matching are arranged on the surface of the dielectric substrate, wherein the ground electrode G and the signal electrode S are used for external and electric connection. The metallic conduction post is used for connecting the signal electrode and an electrode of a photoelectron integrated chip, thereby realizing signal transmission between the signal electrode and the electrode of the photoelectron integrated chip; and the matched resistor connected in series between the signal electrode S and the ground electrode G is connected in parallel with the photoelectron integrated chip to realize non-gold-wire impedance matching, thereby realizing impedance matching of a high-internal-resistance chip. According to the packaging structure, gold wire usage is avoided completely; and the influence on the device performance by a parasitic parameter introduced by the gold wire can be reduced. The packaging structure is suitable for packaging of single-channel or multi-channel integrated chips.

Description

technical field [0001] The invention belongs to the field of optoelectronic / microelectronic devices, and more specifically relates to a packaging structure for optoelectronic integrated chips. Background technique [0002] In the packaging of optoelectronic chips, due to the high resistance characteristics of electro-absorption modulators or other devices, there will be impedance mismatch with the existing 50Ω communication system, which will seriously affect the final performance of the chip. Usually, in order to achieve impedance matching, a 50Ω resistor needs to be connected in parallel to the high-resistance device, which is the most common method in the packaging of high-speed optoelectronic integrated chips. However, when connecting matching resistors in parallel, it is necessary to use a large number of gold wires (especially in multi-channel array integrated chip packages) to respectively connect the transmission line and the electrodes of the high-resistance device,...

AI Technical Summary

Problems solved by technology

This method causes parasitic inductance and parasitic capacitance between the gold wires and between the gold wire and the pad, which seriously affects the transmission and reflection characteristics of the device under high frequency conditions

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