Wafer test pattern yield loss calculation method

Abstract

The invention provides a wafer test pattern yield loss calculation method comprising the following steps: grouping chips included in all test result categories in a wafer bin map to get multiple chip groups; getting multiple characteristic values of each chip group based on the chips included in each chip group; comparing the characteristic values with a model database to get test patterns corresponding to the chip groups; and calculating the yield loss of each test pattern. Therefore, a variety of test patterns in a wafer bin map can be identified automatically, and the yield loss of each test pattern can be calculated automatically.

Description

technical field [0001] The invention relates to a test mechanism of a wafer test pattern, in particular to a method for calculating the loss rate of the wafer test pattern. Background technique [0002] In the semiconductor manufacturing process, a wafer acceptance test (wafer acceptance test, WAT for short) is usually used to perform electrical testing on the wafer. WAT will generate a lot of electrical parameters and values, users can use these electrical parameters and values ​​to evaluate the yield of the wafer under test and discover possible problems in the semiconductor manufacturing process. However, in the semiconductor manufacturing process, when the wafer under test has a low yield rate, sometimes it is not caused by a single accident. In practice, different accident causes will result in different test patterns in the wafer bin map. Therefore, tracking the abnormal condition through the loss rate (Yield Loss) of the test pattern can usually have a good effect. ...

AI Technical Summary

Problems solved by technology

[0003] However, most semiconductor factories still use manual identification to judge the test patterns in the wafer image. This is not only labor-intensive, but also easily leads to deviations...

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