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Electrostatic discharge (ESD) protection structure at chip input/output port and chip

An ESD protection and output port technology, applied in the field of microelectronics, can solve the problems of MOS tube output speed reduction, MOS can not meet the requirements, etc., to achieve the effect of speed improvement

Inactive Publication Date: 2016-10-05
CAPITAL MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, a disadvantage of this method is that the output speed of the MOS tube is greatly reduced due to the addition of a special process level to the MOS tube, which can only reach half of the output speed of the MOS tube without SAB treatment or even 1. / 3
This makes the MOS of this structure unable to meet the requirements in the application of high-speed output ports.

Method used

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  • Electrostatic discharge (ESD) protection structure at chip input/output port and chip

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Embodiment Construction

[0019] figure 1 A schematic structural diagram of an electrostatic discharge (ESD) protection structure for an input / output port of a chip provided by Embodiment 1 of the present invention. like figure 1 As shown, the ESD protection structure of the present invention includes a group of CMOS drive transistors connected between the chip input / output port (PAD) and the internal connection terminal (in) of the chip, and in the group of MOS drive transistors, each MOS transistor A resistor R connected in series between the drain and PAD.

[0020] Specifically, the CMOS driving transistor and the serially connected resistor R in the present invention adopt a multi-finger protection structure, wherein the CMOS driving transistor includes an NMOS transistor and a PMOS transistor. in such as figure 1 In the structure shown, the upper part is a PMOS transistor, and the lower part is an NMOS transistor. Here, both the NMOS tube and the PMOS tube are made by common CMOS process, with...

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Abstract

The present invention relates to an ESD protection structure at a chip input / output port and a chip. The structure comprises a set of complementary metal-oxide-semiconductor (CMOS) driving tubes between the chip input / output port and a chip internal connection terminal, and a resistor in series connection between the drain of each driving tube of the set of CMOS driving tubes and the chip input / output port, wherein the resistors are injection resistors, and parasitic diodes exist between the resistors and the well regions and are used to form an ESD access.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to an electrostatic discharge ESD protection structure of a chip input / output port and a chip. Background technique [0002] Electrostatic discharge (Electrostatic Discharge, ESD) will bring destructive consequences to electronic devices. ESD occurs very quickly with extremely high intensity, and usually generates enough heat to melt the internal circuit of the semiconductor chip, which is one of the main reasons for the failure of integrated circuits. [0003] CMOS is often used as a drive tube for input / output ports. With the continuous development of integrated circuit technology, the feature size of Complementary Metal-Oxide Semiconductor (CMOS) continues to shrink, and Metal-Oxide Semiconductor (Metal-Oxide Semiconductor, The gate oxide thickness of MOS) is getting thinner and thinner, and the current and voltage that MOS tubes can withstand are getting smaller and sm...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02H9/04
Inventor 刘成利陈子贤刘明
Owner CAPITAL MICROELECTRONICS
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