A reusable verification system for eda and fpga for passive tag chips

Abstract

The invention relates to an EDA (electronic design automation) and FPGA (field programmable gate array) reusable verification system for passive tag chips. The EDA and FPGA reusable verification system comprises an EDA environment verification system and an FPGA environment verification system. A reader verilog model (2) and a DUT (device under test) (7) in the EDA environment verification system and a reader verilog model (1-3) and a DUT (1-10) in the FPGA environment verification system can be reused mutually. The EDA and FPGA reusable verification system has the advantages that the readers and verilog codes of tags can be reused in EDA and FPGA verification environments in the verification systems, accordingly, codes for EDA and FPGA are identical, RTL (resistor transistor logic) codes do not need to be modified between the two verification systems, and high risks due to little modification can be prevented.

Description

technical field [0001] The invention relates to an EDA and FPGA reusable verification system for passive tag chips. Background technique [0002] The current mainstream EDA verification system in the industry such as figure 1 As shown, the module DUT to be verified is instantiated in the verification environment, and it is carried out by adding incentives to the DUT and observing the output of the DUT. Such a defect is that if the SV model of the reader written by the verification engineer is defective, it cannot be verified. There are also scenarios that are overlooked by both the verification engineer and the design engineer and are hard to spot. [0003] Current mainstream FPGA verification systems in the industry such as figure 2 As shown, the practical physical product reader communicates with the tag RTL code downloaded to the FPGA board for verification through the antenna. The defect of this system is that all scenarios of the physical product reader are only a sm...

AI Technical Summary

Problems solved by technology

[0002] The current mainstream EDA verification system in the industry such as figure 1 As shown, the module DUT to be verified is instantiated in the verification environment, and it is carried out by adding incentives to the DUT and observing the output of the DUT. Such a defect is that if the SV model of the reader written by the verification engineer is defective, it cannot be verified. There are also scenarios that verification engineers and design engineers ignore at the same time are difficult to find

[0003] Current mainstream FPGA verification systems in the industry such as figure 2 As shown, the practical physical product reader communicates with the tag RTL code downloaded to the FPGA board for verification through the antenna. The defect of this system is that all scenarios of the physical product reader are only a small part of the verification space, and all parameters have been verified. Fixed the latter change is too small or too large, does not meet the standard requirements, and the development progress of the reader may lag behind the development progress of the label, such a verification system is too dependent on the reader manufacturer, which seriously hinders the development progress of the label

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