Embedded type semiconductor chip fan-out type packaging structure and manufacturing method therefor

Abstract

The invention discloses an embedded semiconductor chip fan-out packaging structure and a manufacturing method thereof. The packaging structure includes a semiconductor substrate and a chip. A plurality of conductive pads are arranged on the front side of the chip, and the semiconductor substrate is provided with a receiving groove, and the chip is accommodated in the receiving groove with the front facing outward. A metal post is grown on each conductive pad, and the metal post is higher than the upper surface of the semiconductor substrate. The gap between the receiving groove and the chip, the upper surface and the surroundings of the metal post are filled or covered by an insulating layer. A metal rewiring is connected to the top surfaces of all the metal pillars, and at least one metal rewiring extends beyond the surface of the chip. In the present invention, metal pillars are long on the chip, and the chip and the metal pillars are covered with polymer materials, and then the metal pillars of the chip are exposed by using a planarization process, so as to ensure the flatness of the surface of the package; meanwhile, the size range of the groove can be expanded . The invention also discloses a manufacturing method of the embedded semiconductor chip fan-out packaging structure.

Description

technical field [0001] The invention relates to a chip fan-out packaging structure and a manufacturing method thereof in the technical field of semiconductor packaging, in particular to an embedded semiconductor chip fan-out packaging structure and a manufacturing method thereof. Background technique [0002] The company has always paid attention to the research of chip packaging technology, such as the "Buried Silicon Substrate Fan-Out Type package structure and manufacturing method thereof". However, when the chip is embedded in the silicon substrate, due to process or design reasons, the chip may be lower or higher than the substrate surface, and it is difficult to ensure that all chip surfaces are consistent with the substrate surface. If the height difference is large, the metal circuit on the upper insulating layer will be uneven, increasing the stress on the metal circuit, and there is a hidden danger that the metal circuit will be broken. And when the solder balls ...

AI Technical Summary

Problems solved by technology

However, when the chip is embedded in the silicon substrate, due to process or design reasons, the chip may be lower or higher than the substrate surface, and it is difficult to ensure that all chip surfaces are consistent with the substrate surface

If the height difference is large, it will lead to uneven metal lines on the upper insulating layer, increasing the stress on the metal lines, and there is a hidden danger that the metal lines will be broken

And when the solder balls are added later, there is a height difference between the solder balls on the chip and the solder balls fanned out to the substrate, and there will also be reliability problems when the chip is soldered to the external circuit board

Images