Memory physical layer interface logic for generating dynamic random access memory (dram) commands with programmable latency

Abstract

A plurality of registers (222) implemented in conjunction with the memory physical layer interface (PHY) (140, 205) may be used to store one or more instruction words (300). A training engine (220) implemented in the memory PHY may generate a sequence of full-speed programmable commands (410, 420, 430, 510, 520, 525) for delivery to external memory (210), and based on the one or more delay to delay the command. The full speed programmable command sequence can be generated based on the one or more instruction words.

Description

technical field [0001] The present disclosure relates generally to processing systems, and more particularly, to memory physical layer interfaces in processing systems. Background technique [0002] Processing systems, such as a system on a chip (SOC), use memory to store data or instructions for later use. For example, a SOC may include processing units such as a central processing unit (CPU), a graphics processing unit (GPU), and an accelerated processing unit (APU) may read instructions or data from a memory, perform operations using the instructions or data, And then write the result back to memory. The processing system may include a memory physical layer interface to control access to memory modules, such as dynamic random access memory (DRAM), which may be used to store information such that the stored information may be accessed by the processing unit during operation of the processing system access. The memory physical layer interface in a processing system is co...

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Latency intervals can also be different for different types of DRAM and may change when new DRAM designs or timing standards are introduced

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