Xilinx-FPGA-based multi-gigabit-network flow combination system and realization method thereof

An implementation method and network port technology, applied in the field of network communication, can solve the problems of high hardware cost and software cost, unable to meet the various needs of users, etc. Effect

Inactive Publication Date: 2016-12-14
JUNENG SPECIAL COMM EQUIP CO LTD TOEC GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The above solution will lead to high hardware and software costs. If password protection is required for data transmission, special hardware devices need to be added, which cannot meet the various needs of users.

Method used

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  • Xilinx-FPGA-based multi-gigabit-network flow combination system and realization method thereof
  • Xilinx-FPGA-based multi-gigabit-network flow combination system and realization method thereof
  • Xilinx-FPGA-based multi-gigabit-network flow combination system and realization method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0064] The embodiment of the present invention discloses a method for realizing multi-gigabit network convergence based on Xilinx FPGA, see figure 1 , the Xilinx FPGA-based multi-gigabit network convergence system consists of the following parts: the first MAC module 1, the second MAC module 2, the third MAC module 3, the fourth MAC module 4, the fifth MAC module 5, and the sixth MAC module Module 6, internal processing logic module 7, PCIE high-speed interface module 8, clock module 9, and other external interface logic modules 10.

[0065] see figure 2 , the first MAC module 1 includes: a first gigabit ETMAC core module 11, a first RGMII interface module 12, a first transceiver processing logic module 13, and a first synchronization module 14, which are used to establish a gigabit network for data transceiving .

[0066] The first transceiver processing logic module 13 includes: a first TX module 131 and a first RX module 132 , the first TX module 131 is used for data tra...

Embodiment 2

[0078] The embodiment of the present invention discloses an implementation method of a Xilinx FPGA-based multi-gigabit network convergence system, see Figure 5 , the implementation method includes the following steps:

[0079] 101: After the system is started, the first MAC module 1, the second MAC module 2, the third MAC module 3, the fourth MAC module 4, the fifth MAC module 5, and the sixth MAC module 6 are initialized, and the six MAC modules are respectively Configure the corresponding PHY module accordingly, such as MAC address, flow control settings, etc.;

[0080] 102: Configure the external PHY register through the MDIO (management data interface) bus interface to meet the needs of MAC communication;

[0081] 103: Complete the initialization of the PCIE high-speed interface module 8;

[0082] Wherein, this step is the same as the operation process of step 101, which is not repeated in this embodiment of the present invention.

[0083] 104: The system checks that t...

Embodiment 3

[0088] Combine below Figure 6 The data communication from the network port to the host direction of the implementation method of the Xilinx FPGA-based multi-gigabit network confluence system in embodiment 2 is described in detail, and the first MAC module 1 is used as an example for illustration, see the following description for details:

[0089] 201: The network port receives data, after being processed by the first RX module 132, it enters the bus receiving buffer with an 8-bit width, and generates a data fetch flag every time a frame is full, and notifies the bus to fetch data;

[0090] 202: The receiving bus module 711 extracts data frames from the receiving buffer of the first RX module 132 packet by packet according to the order in which the data arrives, and performs parsing, filtering and other related processing through the data processing module 74;

[0091] 203: The receiving bus module 711 forms a large packet of the processed related network frames and transfers...

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Abstract

The invention discloses a Xilinx-FPGA-based multi-gigabit-network flow combination system and a realization method thereof. The system is composed of six MAC modules, an internal processing logic module, a PCIE high-speed interface module, a clock module, and another external interface logic module. In addition, the realization method includes: a system checks an MAC module ready signal and a PCIE high-speed interface module ready signal and starts transmission work after receiving the two ready signals; after a host operation system is started completely, loop testing is carried out on an internet access corresponding to the MAC module, correctness of a network device is checked, and a network mark is obtained; and bidirectional data communication between the internet access and the host is carried out. According to the invention, a plurality of gigabit MACs are established by using an ETMACIP core; and a plurality of network cards are established by using the MAC and an external PHY way and thus a plurality of gigabit networks are established, thereby meeting a requirement of a fast data processing speed.

Description

technical field [0001] The invention relates to network communication, the physical layer and the data link layer of the network OSI seven-layer model, FPGA program design, and IPcore, in particular to a Xilinx FPGA-based multi-gigabit network convergence system and an implementation method. Background technique [0002] With the development of new technologies such as cloud computing, the Internet of Things, mobile Internet, and big data, and the wide application of data encryption and decryption, the data volume has exploded. There are many data access points and high real-time requirements, requiring the use of multi-gigabit networks. Consolidation of data. [0003] There are many products in the field of multi-gigabit network port design, and various technologies are used, but there are few products that combine data from these gigabit network ports. The general method is to increase the network speed of the host to 10G, then perform multi-channel transmission and recep...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/701H04L12/933
CPCH04L45/245H04L49/10
Inventor 王铁男吴淑艳苏锦绣孟祥臣唐占涛袁静王慧
Owner JUNENG SPECIAL COMM EQUIP CO LTD TOEC GRP
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