Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate frequency

A frequency shift keying and binary technology, which is applied in the direction of frequency modulation carrier system, modulation carrier system, phase modulation carrier system, etc., can solve a lot of problems such as time and difficulty

Active Publication Date: 2016-12-14
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The architecture of Figure 3 (PLL loop modulation) is conceptually simple and well suited for low data rate conversions, but presents difficulties in meeting eye diagrams at USB

Method used

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  • Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate frequency
  • Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate frequency
  • Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate frequency

Examples

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Embodiment Construction

[0011] Example embodiments implement BFSK modulation (such as implementing the USB PD specification) by selecting the appropriate phase of the high frequency clock to produce a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. According to the binary data "1" or "0" to be transmitted, convert "M" or "M+1" clock phases from the high frequency clock to an intermediate clock whose frequency is 2*N of the carrier frequency times, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation therein, and is used to generate the N pulse width modulation (PWM) phases of the waveform operating at the carrier frequency. The N phases are then appropriately weighted to synthesize the output sinusoidal waveform. In some embodiments, significant harmonic content exists only at (2*N-1) harmonics and upwards in the output sinusoidal ...

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Abstract

In described examples, binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock (40) to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency, and M is an integer. Depending on the binary data "1" or "0" to be transmitted (45), "M" or "M+l" clock phases from the high frequency clock are converted (43) to an intermediate clock (44) that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock (44), generated entirely in the digital domain, has the required data modulation in it, and is used for generating (46) N pulse width modulated (PWM) phases (47) of waveforms operating at the carrier frequency. The N phases (47) are then weighed appropriately (48) to synthesize a sine waveform (49) whose lower harmonics are substantially suppressed.

Description

technical field [0001] The present invention relates generally to modulation for data transmission, and more particularly to binary frequency shift keying modulation. Background technique [0002] Binary Frequency Shift Keying (BFSK) is a form of data modulation commonly used in communications technology. For example, the transport architecture used to implement the USB Power Delivery (USBPD) specification must use low power BFSK and must meet current budget requirements including eye diagrams for frequency translation, FCC transmit spectrum, and average transmit power. Such compliance may require excessive structural complexity, excessive circuit area, and onerous testing, debugging, and verification requirements. Figures 1-3 (Prior Art) illustrate a conventional approach to implementing the USB PD specification. [0003] The architecture of Figure 1 (square wave to triangle wave to class A driver) is conceptually simple, but introduces harmonics that require complex on-c...

Claims

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Application Information

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IPC IPC(8): H04L27/10H04L27/22G08C19/18
CPCH03K7/06H04L27/10H04L27/12H04L27/127
Inventor A·S·拉奥A·库达瑞K·苏布拉吉
Owner TEXAS INSTR INC
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