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Fast delay signal cancellation filtering method and device, equipment and storage medium

A time-delayed signal and fast technology, applied in harmonic reduction devices, AC networks to reduce harmonics/ripples, and flicker reduction of AC networks, etc., can solve the problem that the advantages are not obvious, affect the dynamic performance of the system, and the computing power of the controller Weakness and other problems, to achieve the effect of strong ability to filter out harmonics

Pending Publication Date: 2022-02-08
SHANDONG INST OF BUSINESS & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Cascading multiple DSC operators with different delays can accurately extract the positive sequence component of the fundamental wave of the distorted asymmetric voltage. However, the total filtering time is as high as 1 / 2 of the fundamental wave cycle, which affects the dynamic performance of the system.
[0007] In response to this, the document "Phase Locked Loop Based on Improved Filtering and Positive and Negative Sequence Separation Method" proposed an improved DSC method, each operator can eliminate a kind of harmonic more quickly; but when the grid voltage contains multiple harmonics and the control When the computing power of the processor is weak, the advantage of this method is not obvious
The literature "A PLL based on improved filter and sequence detection method" optimizes the number of cascaded DSC operators according to the distortion of the actual grid voltage; however, the filtering time of this method is still greater than 1 / 4 of the fundamental period

Method used

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  • Fast delay signal cancellation filtering method and device, equipment and storage medium
  • Fast delay signal cancellation filtering method and device, equipment and storage medium
  • Fast delay signal cancellation filtering method and device, equipment and storage medium

Examples

Experimental program
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Effect test

Embodiment 1

[0094] The fast delay signal destructive filtering method provided in the embodiment of the present application includes:

[0095] Set the appropriate delay Δt and parameter m, by sampling the three grid voltage signals u(t), u(t–Δt) and u(t–2Δt), based on the vectorial nature of the voltage, the harmonics in the three samples Form vector triangles, such as figure 1 As shown, there is u(t)–u(t–2Δt)=m×ju(t–Δt), thus eliminating the harmonic;

[0096] m is the filter parameter;

[0097] j is the imaginary part in the complex field coordinate system;

[0098] –ju(t–Δt) is the quadrature signal lagging u(t–Δt) by 90°;

[0099] The u(t) is the voltage at the current moment, and u(t-Δt) and u(t-2Δt) are the sampling voltages at two lagging moments.

[0100] In some embodiments, the specific method for setting the appropriate delay Δt and parameter m includes:

[0101] Make the delay Δt=T / n;

[0102] The formula u(t)–u(t–2Δt)=m×ju(t–Δt) is:

[0103]

[0104] Among them, T i...

Embodiment 2

[0126] A fast delay signal destructive filtering device, comprising:

[0127] Voltage sampling module, fast delay signal cancellation operator construction module and time domain calculation module;

[0128] The voltage sampling module: sample grid voltage u(t), u(t–Δt) and u(t–2Δt) three times, the u(t) is the voltage at the current moment, u(t–Δt) and u(t –2Δt) is the sampling voltage at two lag moments;

[0129] The fast delay signal cancellation operator construction module: set the appropriate delay Δt and parameter m, so that the harmonics in the three samples form a vector triangle, then u(t)-u(t-2Δt)=m ×ju(t–Δt);

[0130] Make the delay Δt=T / n;

[0131] The formula u(t)–u(t–2Δt)=m×ju(t–Δt) is:

[0132]

[0133] Among them, T is the fundamental wave period, n is the delay coefficient, is a fast delay signal cancellation operator;

[0134] The time-domain calculation module: based on the orthogonal relationship between the two-phase voltages in the αβ coordinat...

Embodiment 3

[0138] Based on the above embodiments, the FDSC is applied to eliminate the h=6k+1 harmonic. due to h * =1 corresponds to the positive sequence component of the fundamental wave, which needs to be decomposed into several groups h * For the harmonic subset of ≠1, the cascaded FDSC is used to eliminate each group of harmonics one by one. For example, the harmonics such as –5, 7, –17, and 19 can be expressed in the form of h=12k–5 (k=0, ±1, ±2…). Substitute n=12 and h * =–5, then there is m=–1, so as to get FDSC(–1,12), the time domain expression is

[0139]

[0140] Substitute h=-1 into FDSC(-1,12), then there is 2sin(2hπ / n)-m=0. This shows that FDSC(–1,12) not only suppresses the h=12k–5th harmonic effectively, but also eliminates the negative sequence component of the fundamental voltage at the same time. Figure 2 is its vector diagram to eliminate the voltage u β The fundamental negative sequence component u in β2 As an example, u in Figure 2(a) α2 (t–T / 12) with –u...

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Abstract

The invention discloses a fast delay signal cancellation filtering method suitable for a three-phase system, which comprises the steps of setting a delay delta t and a parameter m, sampling three power grid voltage signals u (t), u (t-delta t) and u (t-2 delta t), enabling harmonic waves in three samples to form a vector triangle based on the vector property of voltage, namely, u (t)-u (t-2 delta t) = m * ju (t-delta t), thereby eliminating the harmonic waves, wherein m is a filtering parameter; j is a twiddle factor; -ju (t-delta t) is an orthogonal signal lagged by 90 degrees than u (t-delta t); and u (t) is the voltage at the current moment, and u (t-delta t) and u (t-2 delta t) are two sampling voltages at the lag moment. According to the method, through three times of sampling, one harmonic wave can be eliminated based on any short time delay, and one group of harmonic waves can be inhibited at a time. Compared with a classical time delay method, the method has higher harmonic wave filtering capability.

Description

technical field [0001] The present application relates to the field of grid-connected power generation, and in particular to a fast-delay signal destructive filtering method, device, equipment and storage medium. Background technique [0002] The grid-connected power generation of renewable energy such as solar energy and wind energy uses a phase-locked loop (PLL) to calculate the synchronization information of the grid voltage in real time. Among them, the phase-locked loop (Synchronous Reference Frame PLL, SRF-PLL) based on synchronous rotating coordinate transformation changes the fundamental AC quantity into the DC quantity in the synchronous reference coordinate system through Park transformation, and uses a set of control parameters to calculate the amplitude of the grid voltage, Phase angle and frequency. Different from it, the enhanced phase-locked loop (Enhanced-PLL, EPLL) uses two sets of parameters to estimate the amplitude and phase angle of the voltage respecti...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02J3/01
CPCH02J3/01H02J3/002H02J2203/10Y02E40/40
Inventor 李希年梁文科金杰
Owner SHANDONG INST OF BUSINESS & TECH
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