Binary frequency shift keying with data modulated in the digital domain and carrier generated from an intermediate frequency

Abstract

Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

Description

technical field [0001] The present invention relates generally to modulation for data transmission, and more particularly to binary frequency shift keying modulation. Background technique [0002] Binary Frequency Shift Keying (BFSK) is a form of data modulation commonly used in communication technology. For example, the transmission architecture used to implement the USB Power Delivery (USBPD) specification must use low-power BFSK and must meet current budget requirements including eye diagrams for frequency conversion, FCC transmission spectrum, and average transmission power. Such compliance may require excessive structural complexity, excessive circuit area, and onerous testing, debugging, and verification requirements. Figure 1-Figure 3 (Prior Art) shows a conventional approach to implementing the USB PD specification. [0003] figure 1 (square wave to triangle wave to class A driver) architecture is conceptually simple, but introduces harmonics that require complex...

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Problems solved by technology

image 3 The architecture (PLL loop modulation) is conceptually simple and well suited for low data rate conversions, but presents difficulties in meeting eye diagrams at USBPD compatible data rates (e.g., 320kbps) and requires a significant amount of time to Design, test and calibration, especially with regard to controlling PLL (Phase Locked Loop) bandwidth

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