Integrated circuits with embedded double-clocked components

Abstract

The application discloses an integrated circuits with embedded double-clocked components. An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion of the functional blocks on the integrated circuit may operate at a 2 times data rate that is double the normal data rate. To support this type of architecture, the integrated circuit may include clock generation circuitry that is capable of providing double pumped clock signals having clock pulses at rising and falling edges of the core clock signal, data concentration circuitry at the input of the 2 times functional blocks, and data spreading circuitry at the output of the 2 times functional blocks.

Description

[0001] This application claims priority to US Patent Application No. 14 / 729,389 filed June 3, 2015, which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates to programmable integrated circuits, and more particularly to programmable integrated circuits with double clocked embedded blocks. Background technique [0003] Programmable integrated circuits such as programmable logic devices (PLDs) typically include programmable logic blocks, random access memory (RAM) blocks, and digital signal processing (DSP) blocks. The programmable logic block contains programmable memory elements loaded with configuration data that configure the programmable logic block for implementing custom user functions. [0004] Typically, different types of blocks on a programmable logic device operate using the same clock frequency (ie, programmable logic blocks, RAM blocks, and DSP blocks are clocked at the same rate). To improve the overall pe...

AI Technical Summary

Problems solved by technology

However, such a scheme would require redesigning the DSP blocks to operate at twice the frequency relative to the rest of the system, which can be expensive and challenging to implement

Additionally, the routing connections between the 500MHz DSP blocks and the 250MHz soft logic are often complex and introduce significant routing pressure, which can potentially reduce any performance gains provided by the faster DSP blocks

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