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A method of manufacturing a semiconductor device

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as extremely high requirements for overlay accuracy, improve overlay tolerance, improve uniformity and accuracy, improve The effect of overlay tolerance

Active Publication Date: 2019-04-23
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The invention aims to solve the problem that the existing imaging technology requires extremely high overlay precision, and provides a manufacturing method of a semiconductor device, which can effectively increase the overlay tolerance of the overlay process, so as to improve the uniformity and accuracy of key graphics

Method used

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  • A method of manufacturing a semiconductor device
  • A method of manufacturing a semiconductor device
  • A method of manufacturing a semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] In this embodiment, the layer to be processed may be a layer to be etched or a layer to be ion implanted. In the following specific embodiments, the layer to be etched is an interlayer dielectric layer as an example for description. The pattern of the first mask layer formed by the method of the embodiment etches the interlayer dielectric layer so as to subsequently form a metal interconnection structure.

[0054] Such as figure 1 As shown, in this exemplary embodiment, the pattern to be finally formed is a metal interconnection layer, and the metal interconnection layer includes two patterns with different periods and sizes, such as 410 patterns and 420 patterns.

[0055] The following list is prepared as figure 1 Design shown figure 1 The pattern can be completed through the following specific embodiments.

[0056] Step S01, providing the substrate 50, on which the layer to be processed 40, the first mask layer 30, and the first pattern 210 are sequentially formed,...

Embodiment 2

[0087] In this embodiment, different from the first embodiment, through holes and interconnection structures can be formed in the layer to be processed at the same time. Only the parts different from the first embodiment will be described below, and the same parts will only be briefly explained.

[0088] Such as Figure 30 to Figure 31 As shown, it is the pattern to be realized in this embodiment, wherein the metal interconnect pattern 410 and the through hole 420, that is, in the layer 40 to be processed, in addition to forming the metal interconnect pattern 410, it is also necessary to form the corresponding pattern in the layer 40 to be processed A via hole 420 for interconnection with the previous layer is formed in the position to realize interconnection between different layers. Wherein, the through hole 420 needs to be precisely aligned with the set position of the previous layer and the set position of the metal interconnection in the layer 40 to be processed.

[0089...

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Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises: a substrate is provided and a to-be-processed layer, a first mask layer and a first pattern are formed on the substrate successively, wherein the first pattern includes a key dimension pattern; a first barrier layer is formed, wherein the thickness of the first barrier layer does not exceed the half of the interval between closest patterns in the first pattern; a groove is filled to form a second barrier layer having a flat surface and a second pattern is formed on the surface; etching is carried out by using the second pattern as a mask until the to-be-processed layer is exposed and a first mask layer pattern is formed in the first mask layer; and the to-be-processed layer is processed by using the first mask layer pattern as a mask. According to the method, when the overlay tolerance exceeds the half of the key dimension, for the gap generated by the overlay deviation in the prior art, the to-be-processed layer can be protected from not being affected under the slit because of the first barrier layer, so that the tolerance of the overlay is improved and thus uniformity and accuracy of the key pattern are improved effectively.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor device. Background technique [0002] As the process node of semiconductor chips decreases to 20 nanometers and below, the transfer of key layers has become more and more important, especially the metal layer fabrication of memory back-end processes, Fin fabrication of fin transistors (FinFETs), etc. [0003] As the period of the key layers to be transferred becomes smaller and smaller, manufacturing accuracy and overlay accuracy become one of the main factors restricting the yield rate in semiconductor manufacturing. For example, for the figure 1 The pattern shown is transferred to the layer to be etched, and the traditional SADP manufacturing process is as follows Figures 2 to 7 As shown, first, the layer to be etched 40, the first mask layer 30, and the first pattern 210 are sequentially formed on the substrate 50 includi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
CPCH01L29/66795
Inventor 张利斌韦亚一殷华湘
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI