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Accumulator-based low-complexity digital matched filtering method

A low-complexity, matched-filtering technology, applied in the direction of digital technology networks, impedance networks, electrical components, etc., can solve the problems of high resource consumption and high system complexity of digital matched filters, and achieve low resource consumption and simple implementation process Effect

Inactive Publication Date: 2017-01-04
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0004] The purpose of the present invention is to solve the problem that digital matched filter (DMF) resource consumption is too large and system complexity is too high under the situation of system low throughput, has proposed a kind of accumulator-based low-complexity digital matched filter method, uses Accumulator structure and full serial operation to save resources occupied by matched filters and reduce system complexity

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  • Accumulator-based low-complexity digital matched filtering method

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Embodiment

[0020] In an exemplary embodiment of the invention, a low complexity digital matched filter for a system is provided. The system mainly includes two dual-port RAMs to realize the ping-pong buffer structure, and a multiplier and an accumulator to realize the convolution operation in matched filtering. In addition, there is a single-port ROM for storing spreading codes. The combination of all levels of the system can realize the lower resource consumption of the system in the case of low throughput.

[0021] The specific working principle of the present invention is described below in the specific environment of a certain system.

[0022] Such as figure 1 As shown, in a certain system, the front-stage input of DMF is a Hz signal. Assuming that the working clock rate of the FPGA is b Hz, in order to enable the DMF to work at the sampling rate of b Hz, the rate conversion from a Hz to b Hz must first be completed through a pair of dual-port RAMs with a ping-pong structure (“slo...

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Abstract

The invention relates to an accumulator-based low-complexity digital matched filtering method, which belongs to the field of digital signal processing technologies. The accumulator-based low-complexity digital matched filtering method is designed based on an accumulator structure and full-serial operation, is simple in implementing process, and consumes few resources; and for a low-throughput system with multi-path data, the accumulator-based low-complexity digital matched filtering method can significantly reduce resource consumption and complexity of the system without decreasing performance of the system.

Description

technical field [0001] The invention relates to a low-complexity digital matched filtering method based on an accumulator, belonging to the technical field of digital signal processing. Background technique [0002] Digital matched filters (DMFs) are an important part of digital signal processing blocks in communication systems and measurement systems. Code phase acquisition, despreading and demodulation all depend on the output of DMF. For a direct sequence spread spectrum communication system with a high code rate, in order to ensure that the DMF has a sufficient throughput, it is usually necessary to use a multi-stage full pipeline structure and a parallel adder tree algorithm to achieve it. DMF often becomes the program at the receiving end of the entire communication system. Resource bottleneck. [0003] For a low-throughput system with multiple channels of data, if each channel of data is implemented using the traditional DMF's multi-level full-pipeline structure and...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H17/02
Inventor 徐昂刘策论韩航程卜祥元王帅鲁楠罗婧涂水平代计博
Owner BEIJING INSTITUTE OF TECHNOLOGYGY