Accumulator-based low-complexity digital matched filtering method
A low-complexity, matched-filtering technology, applied in the direction of digital technology networks, impedance networks, electrical components, etc., can solve the problems of high resource consumption and high system complexity of digital matched filters, and achieve low resource consumption and simple implementation process Effect
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[0020] In an exemplary embodiment of the invention, a low complexity digital matched filter for a system is provided. The system mainly includes two dual-port RAMs to realize the ping-pong buffer structure, and a multiplier and an accumulator to realize the convolution operation in matched filtering. In addition, there is a single-port ROM for storing spreading codes. The combination of all levels of the system can realize the lower resource consumption of the system in the case of low throughput.
[0021] The specific working principle of the present invention is described below in the specific environment of a certain system.
[0022] Such as figure 1 As shown, in a certain system, the front-stage input of DMF is a Hz signal. Assuming that the working clock rate of the FPGA is b Hz, in order to enable the DMF to work at the sampling rate of b Hz, the rate conversion from a Hz to b Hz must first be completed through a pair of dual-port RAMs with a ping-pong structure (“slo...
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