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A DDR timing analysis method, device and system

A technology of timing analysis and timing, applied in static memory, instruments, etc., can solve the problems of cost reduction, low test accuracy, poor setup time and hold time value, etc., and achieve the effect of cost reduction

Active Publication Date: 2020-04-03
GUANGDONG VTRON TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] A DDR timing analysis method, device, and system provided by the embodiments of the present invention solve the problem that the current DDR test method is difficult to test the worst set-up time and hold time values ​​when measuring the set-up time and hold time of DDR, resulting in accurate testing. Low-degree technical problems, and use Labview software to conduct DDR timing analysis through ordinary oscilloscopes, greatly reducing costs

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  • A DDR timing analysis method, device and system
  • A DDR timing analysis method, device and system
  • A DDR timing analysis method, device and system

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Embodiment Construction

[0053]A DDR timing analysis method, device, and system provided by the embodiments of the present invention solve the problem that the current DDR test method is difficult to test the worst setup time and hold time value when measuring the setup time and hold time of DDR, which leads to the accuracy of the test. Low-level technical problems, and the use of Labview software to perform DDR timing analysis through ordinary oscilloscopes, greatly reducing costs.

[0054] In order to make the purpose, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the following The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by per...

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Abstract

Embodiments of the present invention disclose a method, device and system for DDR timing analysis, which solves the problem that the current DDR test method cannot measure the setup time and hold time of DDR, and it is difficult to test the worst setup time and hold time values, resulting in accurate testing. Low-level technical problems, and the use of Labview software to perform DDR timing analysis through a common oscilloscope, greatly reduces costs. The DDR timing analysis method according to the embodiment of the present invention includes: performing a read operation or a write operation on the DDR, and saving the DQ and DQS waveform diagrams of the DDR; using Labview software to perform a data separation operation on the DQ and DQS waveform diagrams, and removing three corresponding to the DQS signal. The corresponding eye diagram is formed for the DQS signal with the tri-state signal removed, and the timing of the DDR is determined according to the eye diagram.

Description

technical field [0001] The invention relates to the technical field of DDR testing, in particular to a DDR timing analysis method, device and system. Background technique [0002] DDR=Double Data Rate double rate synchronous dynamic random access memory. Strictly speaking, DDR should be called DDR SDRAM, and people are used to calling it DDR. Among them, SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory, that is, synchronous dynamic random access memory. DDR SDRAM is the abbreviation of Double Data Rate SDRAM, which means double-rate synchronous dynamic random access memory. Now DDR technology has been developed to DDR 3, theoretically the speed can support up to 1600MT / s. The DDR bus has a large number of traces, high speed, complex operation, and difficult detection, which brings great challenges to testing and analysis. DDR essentially doubles the speed of SDRAM without increasing the clock frequency. It allows data to be read on the rising and fall...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
CPCG11C29/56004G11C29/56016
Inventor 黄世民
Owner GUANGDONG VTRON TECH CO LTD
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