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Fault control for eeprom type memory devices

A technology of memory and read-only memory, which is applied in the field of memory, and can solve problems such as preventing low failure, preventing, and memory encountering failure

Active Publication Date: 2021-05-28
STMICROELECTRONICS (ROUSSET) SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] Also, the lower limit of the POR circuit may be correct for ensuring power on power-on reset, but may be too low for preventing glitches
[0016] For example, in the case of a slow drop in voltage from a value of 5V, if data is exchanged at 20MHz, a memory operating at 20MHz below 5V is at risk of encountering a failure
Also, such faults will not be prevented by a POR circuit

Method used

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  • Fault control for eeprom type memory devices
  • Fault control for eeprom type memory devices
  • Fault control for eeprom type memory devices

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0044] figure 1 There is shown an EEPROM memory device DIS of conventional structure known per se, powered by a power supply unit ALIM and associated with a power-on reset circuit POR, according to the invention.

[0045] The device DIS has a memory map PM of memory cells CEL and a conventional write circuit MECR, row and column decoders DECX and DECY, a bit line latch VBL contained in the decoder DECX and a read circuit with a sense circuit amplifier AMPL , has a general structure known per se.

[0046] In this exemplary embodiment, the device DIS similarly has an error correction code mechanism MECC, with a conventional structure known per se.

[0047] For example, the device DIS similarly comprises a controller MCM, a logic circuit of conventional structure capable of activating, inter alia, various circuits such as the write circuit MECR, the read circuit AMPL and the error correction code mechanism MECC.

[0048] The memory device DIS likewise has test modules MTEM ( 1 )...

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Abstract

Provides fault control for EEPROM type memory devices. A method for checking the operation of a device of the Electrically Erasable Programmable Read Only Memory type powered by a supply voltage and associated with a power-on reset circuit. The method includes: performing at least one trial operation corresponding to a phase of operation of the device identified as a phase prone to failure if the supply voltage drops below a given value; performing during operation of the memory device at least a test operation; and analyzing the results of the test operation to detect any failures prevented by the reset circuit.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from French Application No. 1558859 filed September 21, 2015, which is hereby incorporated by reference. technical field [0003] Embodiments and embodiments of the present invention relate to memory, in particular non-volatile memory of the electrically erasable programmable type (EEPROM), in particular the detection of any fault in the memory. Background technique [0004] The invention is particularly, but not limited, applicable to memories capable of operating over a wide range of supply voltages, including low voltages (eg, between 1.6V and 5.5V). [0005] The use of a power-on-reset circuit, generally denoted "POR," is common in EEPROM-type memory devices. [0006] When the supply voltage reaches the specified minimum operating value, the POR circuit generates a reset signal, which is especially applicable to the registers of the functional circuits associated with it. This ma...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/42G11C16/22H03K17/22
CPCG11C16/225G11C29/42H03K17/22G11C7/20G11C2029/0407G11C2029/0411G11C16/10G11C16/26G11C16/30G11C29/4401
Inventor F·塔耶M·巴蒂斯塔
Owner STMICROELECTRONICS (ROUSSET) SAS