Page buffer circuit and control method of non-volatile memory, and memory

Abstract

A page buffer circuit and a control method of a nonvolatile memory and a memory are disclosed. The page buffer circuit includes a first latch, a reading circuit, and a selective 1-setting circuit used for adjusting the potential of a determination node. The determination node is between the reading circuit and the selective 1-setting circuit. The first latch is suitable for memorizing data from external I / O and includes a first latch point and a second latch point. The selective 1-setting circuit is coupled to the first latch point through a first input end, is coupled to the second latch point through a second input end, and is coupled to the determination node through an output end. After the reading circuit reads data of a memory element of the nonvolatile memory to the determination node, under the control of a second voltage source and determination point setting enable signal, the determination node is subjected to 1 setting operation according to the data of the first latch point of the first latch. The above scheme can reduce the area of the page buffer circuit and improve circuit reliability.

Description

technical field [0001] The invention relates to the field of circuit technology, in particular to a nonvolatile memory page buffer circuit, a control method, and a memory. Background technique [0002] NAND flash memory is a non-volatile storage technology, that is, it can still save data after power failure. Compared with other flash memories, it is one of the most effective solutions to achieve large capacity and low cost. The read and write operations of the storage array of the non-volatile memory are in units of pages, and the programming operation data for the storage array comes from external I / O, and is transmitted to the page buffer circuit of the non-volatile memory, and finally programmed into the storage in the storage element of the array. [0003] figure 1 It is a page buffer circuit in the prior art, refer to figure 1 As shown, if the external I / O data is 1, then SLR1 is 1, indicating that programming is prohibited, and the memory element is kept in an eras...

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Problems solved by technology

[0004] figure 1 The circuit 10 in the page buffer circuit of the shown prior art has completed the operation of said selective setting, yet, because the page buffer circuit in the prior art adopts the circuit 10, it is easy to Leakage and large area problems

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