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A Hardware Implementation Method and Circuit of Additive Mask Against Energy Analysis Attack

An energy analysis attack and additive masking technology, which is applied in the field of information security chip design, can solve the problems of large ROM consumption and high cost, and achieve the effects of avoiding information leakage, simple structure, and easy execution

Active Publication Date: 2019-09-06
SHANGHAI AISINOCHIP ELECTRONICS TECH
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Problems solved by technology

[0006] The purpose of the present invention is to provide a hardware implementation method and circuit for resisting energy analysis attacks of an additive mask, so as to solve the problem that the existing MASK masking method of the additive circuit needs to consume a large amount of time due to only table lookup operations. ROM, the problem of high cost

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  • A Hardware Implementation Method and Circuit of Additive Mask Against Energy Analysis Attack
  • A Hardware Implementation Method and Circuit of Additive Mask Against Energy Analysis Attack
  • A Hardware Implementation Method and Circuit of Additive Mask Against Energy Analysis Attack

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Embodiment Construction

[0029] In order to better illustrate the present invention, the present invention will be described in detail with preferred embodiments and accompanying drawings, specifically as follows:

[0030] This embodiment provides a hardware implementation circuit of an additive mask against energy analysis attacks. The circuit is used for calculating the sum of addends with a mask, and obtaining the sum with a mask, so that no mask removal operation will occur in the process of calculating the addend. Specifically, the finite field GF(2 n ) in which the two addends are a and b respectively, and m is GF(2 n ) field of random numbers. The sum of the two numbers a and b is recorded as sum, that is, the following formula is established:

[0031] sum=a+b (1)

[0032] Among them, a, b, sum are GF(2 n ), "+" is defined as the addition modulo n operation.

[0033] Then a, b mask method is as follows

[0034] a^m=am (2)

[0035] b^m=bm (3)

[0036] Among them, "^" is defined as a bit...

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Abstract

The invention provides an energy analysis attack resistant addition mask hardware implementation method and circuit. The method comprises the following steps of S1.setting an input of an addition mask circuit as addend data after a mask and a random number m, wherein the random number m is a mask of the addend data after the mask; and S2.adopting the addition mask circuit to carry out n-stage serial carry addition on the addend data after the mask, and carrying out XOR on a carry of the last bit sum and a bit of current addend data to obtain addends and data with the mask when a sum of bits is computed. The addition mask circuit corresponding to the method has no mask removing operation in a computing process, the mask operation of modulo-n addition operation on GF(2<n>) domain is realized, and n is suitable for any integer which is greater than and smaller than 0.

Description

technical field [0001] The invention relates to the technical field of information security chip design, in particular to an additive mask hardware implementation method and circuit for resisting energy analysis attacks, which are widely used in highly secure encryption computing equipment. Background technique [0002] Nowadays, human society is moving towards a highly information age, and people's requirements for communication capabilities are increasing. How to realize "Anyone can transmit any information to any other person at any time and any place" is the goal pursued by modern communication networks. Mobile communication technology is the key technology to realize this goal. Smart mobile terminals have gradually become popular and become an information processing center that integrates communication, personal business processing, payment, and data storage. The security of mobile smart terminals has attracted widespread attention. [0003] Mobile smart terminals al...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L9/00H04L9/08
Inventor 朱念好周玉洁谭永伟
Owner SHANGHAI AISINOCHIP ELECTRONICS TECH
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