FIFO data balanced output method and output device thereof

Abstract

The invention discloses an FIFO data balanced output method and an output device thereof. The output method comprises the steps that according to a data writing rate, clock reading frequency of data reading and data reading bit width, data output effective signal ratio is calculated; after simplification, the obtained data output effective signal ratio is the simplest irreducible fraction; and according to the simplest irreducible fraction, a reading enable signal of FIFO and a data output indicator signal are obtained. The method is capable of achieving balanced output for the data output of FIFO, reducing the amount of memory in downstream and therefore resources are saved. Besides, data delay is accordingly reduced because memory space decreases.

Description

technical field [0001] The invention relates to the communication field, in particular to a FIFO data equalization output method and an output device thereof. Background technique [0002] In the field of communication, FIFO (First In First Output) is widely used. Its main function is to realize data buffering, data transfer across clock domains, and data unpacking and packet processing. [0003] The working principle of FIFO is as follows: the input data is written into the FIFO according to the write enable signal in the write clock domain; under the action of the read clock domain, the data is output according to the read enable signal, the order of the output data and the write order Relevant; the data written first, read out first (that is, first in first out). [0004] In the actual FIFO module, in order to avoid data overflow or read out invalid data, it is also necessary to output an empty-full signal or an almost-empty-almost-full signal according to the amount of ...

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Problems solved by technology

[0010] In view of the deficiencies in the prior art above, the object of the present invention is to provide a FIFO data balanced output method and an output device thereof, aiming at solving the problem of FIFO unbalanced output in the prior art

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