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Dual-channel satellite navigation anti-disturbing A/D chip

A satellite navigation, dual-channel technology, applied in the field of digital-analog hybrid chips, can solve the problems of using confidentiality risks, embargoes, etc., and achieve the effects of high conversion capacity, reduced area, and accurate power statistics.

Inactive Publication Date: 2017-05-31
NO 20 RES INST OF CHINA ELECTRONICS TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 2. The AD9288 chip and FPGA are all imported components, which are directly used in the navigation system. There are risks in the use of confidentiality and may face the risk of an embargo
This processing method is only applicable to scenarios such as static interference and deceptive interference. However, with the increasingly complex navigation electromagnetic environment, complex application scenarios such as multiple interference, large dynamic interference, and combined interference put forward higher requirements for the ability to resist narrowband interference.

Method used

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  • Dual-channel satellite navigation anti-disturbing A/D chip
  • Dual-channel satellite navigation anti-disturbing A/D chip
  • Dual-channel satellite navigation anti-disturbing A/D chip

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Embodiment Construction

[0021] The present invention will be further described below in conjunction with the accompanying drawings and embodiments, and the present invention includes but not limited to the following embodiments.

[0022] The invention is oriented to the design of miniaturized satellite navigation receivers such as handheld and vehicle-mounted receivers, and can realize the functions of intermediate frequency signal reception, analog-to-digital conversion and narrow-band interference processing of different navigation systems such as dual-channel Beidou and GPS through configuration.

[0023] The dual-channel anti-jamming AD chip of the present invention is integrated with dual-channel 10bitA / D, dual-channel digital signal transmission channels, and a working mode configurator; wherein the A channel is specially designed for the RNSS system, the working system is fixed, and can work in direct (not Anti-interference processing), anti-interference and off three working states. Channel B...

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Abstract

The invention provides a dual-channel satellite navigation anti-disturbing A / D chip, comprising a two paths of 10 bit A / D, two paths of digital signal transmission channels and a working mode configurator; an A channel in the two paths of digital signal transmission channels is specific to an RNSS system, and worked under different states including direct connection, anti-disturbance or closing state; a B channel is specific to RNSS, RDSS or GPS system, and worked at different states including direct connection, anti-disturbance or closing state; the working state of the A channel and the working system and the working state of the B channel are configured by the working mode configurator. The dual-channel satellite navigation anti-disturbing A / D chip can independently receive the simulated medium frequency signals of RNSS, RDSS, GPS and other different satellite navigation systems; the floating of signal energy is stable, and the carrier to noise ratio is improved.

Description

technical field [0001] The invention belongs to the technical field of electronic components, in particular to a digital-analog hybrid chip. Background technique [0002] In the traditional satellite navigation receiver, the analog-to-digital conversion part usually uses imported A / D chips such as AD9288. The anti-narrowband interference function depends on the frequency of the satellite. The Beidou B3 frequency point can be realized by using the A / D+FPGA architecture. GPS usually adopts the array antenna + multi-A / D+FPGA, which is compatible with the wideband interference processing method. Among them, the anti-interference processing circuit adopts a processing method based on LMS (adaptive filtering). This receiver structure has the following problems: [0003] 1. FPGA is a high-power consumption component, which accounts for a large part of the total power consumption of the entire receiver, and the packaging volume is also larger than that of ordinary IC chips. Due t...

Claims

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Application Information

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IPC IPC(8): G01S19/37
CPCG01S19/37
Inventor 张帆胡霄舒钰张文华操炜鼎陈永良
Owner NO 20 RES INST OF CHINA ELECTRONICS TECH GRP
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