A Method for Determining the Failure Location of Semiconductor Devices
A technology for semiconductors and devices, applied in the field of determining the failure position of semiconductor devices, can solve the problems of low efficiency and easy to find wrong targets, and achieve the effect of high efficiency
Active Publication Date: 2020-04-17
CSMC TECH FAB2 CO LTD
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Problems solved by technology
[0005] The existing method is inefficient and easy to find the wrong target; if there is no difference in the graphics around the target, it cannot be used, such as in a dense hole area, so it is necessary to improve the current method of determining the position to eliminate the above-mentioned problems
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[0026] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.
[0027] It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
[0028] It will be understood that when an element or layer is referred t...
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The invention relates to a method for determining a failure position of a semiconductor device. The method comprises the steps that S1) failure position analysis is carried out on the semiconductor device to search for a target position; S2) first identifications are prepared in the plane where the target position is located and in the surrounding of the target position to mark the target position; S3) the target position is located by taking the first identifications as marks, a slice sample including the target position is prepared in the semiconductor device, the bottom of the slice sample is exposed, and a second identification is prepared in the exposed bottom to locate the target position in failure analysis; S4) the slice sample including the target position and the second identification is separated from the semiconductor device to obtain an independent slice sample; and S5) the target position is determined according to the position of the second identification, and TEM analysis is carried out on the target position.
Description
technical field [0001] The invention relates to the field of semiconductors, and in particular, the invention relates to a method for determining the failure location of a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. With the continuous reduction of device size, it brings great challenges to many aspects such as manufacturing and design. The stability and yield of devices have become an important factor to measure the performance of semiconductor devices. [0003] In the failure analysis of the device, if the customer provides the failure analysis address or the failure location can be determined by EFA method analysis, Focused Ion beam (FIB) slices can be analyzed. If no abnormalities are found in the FIB slices, it is necessary to conduct For transmis...
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IPC IPC(8): H01L21/66
CPCH01L22/30
Inventor 李晓丽王金成孙威王佳龙
Owner CSMC TECH FAB2 CO LTD