5 results about "Tem analysis" patented technology

The application discloses a FinFET structure slicing analysis method based on FIB and TEM, and relates to the technical field of semiconductor process detection and analysis. In order to solve the problem of the deficiency of traditional detection technology in resolution and accuracy caused by the complexity of the three-dimensional nano structure of the FinFET device, the application realizes high-precision analysis of the FinFET device by optimizing the whole process of sample pretreatment, FIB processing and TEM analysis. The application utilizes the combination of FIB accurate processing and TEM high-resolution imaging to accurately measure the fin structure morphology, multi-layer film thickness and composition distribution. The application reduces sample damage through processes such as PI conductive adhesive treatment and low-energy ion cleaning, and combines a dynamic parameter optimization mechanism to ensure the sample integrity in the processing and detection process. The application introduces three-dimensional reconstruction and structure-performance correlation analysis, which not only can stereoscopically present the structure characteristics of the FinFET, but also can simulate the influence of parameters such as fin pitch and gate coverage length on the device performance.

The application discloses a TEM sample preparation method, comprising the following steps: step one, providing a chip sample with a metal protective layer formed on a first surface; step two, fixing the chip sample on a sample stage of a FIB system; step three, performing first FIB cutting on the metal protective layer along a first direction to form a groove; the first direction is a width direction of the TEM sample, a second direction is perpendicular to the first direction; the groove extends along the first direction; on a section along the second direction, an inner side surface of the groove is arc-shaped, so that the thickness of the metal protective layer in the groove area gradually changes; step four, performing second FIB cutting along a third direction to thin the chip sample and form a TEM sample; the third direction points from the metal protective layer to the chip sample; the thickness of the metal protective layer is used to adjust a cutting speed, so that the width of the TEM sample gradually changes and an optimal observation area is obtained. The application can realize accurate control on the thickness of the TEM sample, thereby improving the TEM analysis quality.

The application provides a TEM sample preparation method, comprising the following steps: step one: extracting a sample containing a first target position and a second target position from a chip surface; step two: bonding the sample to a first welding column of a copper carrier; step three: cutting the sample to separate the first target position and the second target position, and cutting off the first target position; step four: bonding the first target position cut off in step three to a second welding column of the copper carrier; step five: cutting the sample remaining on the first welding column to cut off the second target position, and bonding the sample cut off to a third welding column of the copper carrier; and step six: etching the first target position and the second target position respectively until a TEM analysis thickness is reached. The application can simultaneously prepare TEM samples of two target positions with a horizontal distance of less than 370 nm, and overcomes the defect that two close-range cross-section samples cannot be simultaneously prepared by a traditional method.

The invention discloses a FinFET structure slice analysis method based on FIB and TEM, and relates to the technical field of semiconductor process detection and analysis. The objective of the invention is to solve the problem that a traditional detection technology is insufficient in resolution and accuracy due to the complexity of a three-dimensional nano structure of a FinFET device. By optimizing the whole process of sample pretreatment, FIB processing and TEM analysis, high-precision analysis of a FinFET device is realized, and the morphology of a fin-shaped structure, the thickness of a multi-layer film and component distribution are accurately measured by combining FIB accurate processing and TEM high-resolution imaging; the sample damage is reduced through PI conductive adhesive treatment, low-energy ion cleaning and other processes, and the integrity of the sample in the processing and detection process is ensured in combination with a dynamic parameter optimization mechanism; three-dimensional reconstruction and structure-performance correlation analysis are introduced, so that the FinFET structure characteristics can be presented in a three-dimensional manner, and the influence of parameters such as fin spacing and gate coverage length on the device performance can be simulated.

A substrate is provided comprising a patterned region defined by a given topography on its surface. The substrate will be processed to obtain a TEM sample in the form of a slice of the substrate. According to the method of the invention, a conformal layer of contrast material is deposited on the topography by depositing a layer of contrast material on a local target region of the substrate separated from the patterned region. The material is deposited by Electron Beam Induced Deposition (EBID). The deposition parameters, the thickness of the layer deposited in the target region and the distance of said target region to the patterned region are such that a conformal layer of contrast material is formed on the topography of the patterned region. This is followed by the deposition of a protective layer which does not destroy the topography in the patterned region as the topography is protected by the conformal layer. The TEM sample is prepared in a manner known in the art, for example by FIB. The conformal contrast layer provides a good contrast with the protective layer, thereby allowing a high quality TEM analysis.