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Multi-engine implementation method and system based on DPI in FPGA

An implementation method and system implementation technology, applied in the transmission system, digital transmission system, data processing input/output process, etc., can solve the problems of smooth expansion of performance, performance bottleneck, disadvantage of single engine, etc.

Inactive Publication Date: 2017-06-27
北京浩瀚深度信息技术股份有限公司
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Problems solved by technology

However, due to the delay in external memory access and the difference in internal processing speed, it is easy to become a performance bottleneck, and a single engine is not conducive to the smooth expansion of performance.
[0003] In summary, there are obviously inconveniences and defects in the actual use of the existing technology, so it is necessary to improve

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  • Multi-engine implementation method and system based on DPI in FPGA
  • Multi-engine implementation method and system based on DPI in FPGA
  • Multi-engine implementation method and system based on DPI in FPGA

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Embodiment Construction

[0033] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0034] see figure 1 and figure 2 , the present invention provides a multi-engine implementation system based on DPI in FPGA, the system 100 is a system for processing messages based on FPGA and engine, which includes:

[0035] The message forwarding module 10 is configured to forward the message at a wire speed based on the high-speed clock of the FPGA.

[0036] The information extraction module 20 is configured to extract the five-tuple information of the message. The five-tuple information in the present invention includes the source IP address, source port, destination IP address, destinatio...

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Abstract

The invention is suitable for the field of message detection and processing technology, and provides a multi-engine implementation method based on DPI in FPGA. The method comprises the following steps: implementing wire-speed forwarding on a message based on a high-speed clock of the FPGA; extracting the quintuple information of the message; calculating the quintuple information by using a Hash compression algorithm; and configuring the message to a corresponding engine for processing according to the calculation result. The invention correspondingly provides a multi-engine implementation system based on the DPI in the FPGA. Thereby, according to the multi-engine implementation method and system provided by the invention, the design difficulty and performance requirements of each engine can be reduced through distribution processing of multiple engines, and the storage rate and delay requirements of an off-chip memory can also be reduced.

Description

technical field [0001] The invention relates to the technical field of message detection and processing, in particular to a multi-engine implementation method and system based on DPI in FPGA. Background technique [0002] DPI (Deep Packet Inspection) is a packet-based deep inspection technology. At present, the mainstream DPI technology is divided into two categories, one uses software method, and uses multi-core / NP to detect. The other uses hardware such as FPGA for detection. If the software method is used for processing, it cannot meet the requirements of large-flow line-speed processing. For DPI processing at wire speed under large traffic, the current mainstream is to use hardware. FPGA-based DPI technology is relatively simple if a single engine is used to process packets. However, due to the delay in external memory access and the difference in internal processing speed, it is easy to become a performance bottleneck, and a single engine is not conducive to smooth ...

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Application Information

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IPC IPC(8): H04L12/803H04L12/861H04L29/06G06F3/06
CPCH04L47/125G06F3/0659H04L49/9063H04L69/04
Inventor 沈璐于华陈陆颖
Owner 北京浩瀚深度信息技术股份有限公司