A method of manufacturing a semiconductor device

Abstract

The invention provides a manufacturing method for a semiconductor device, and relates to the technical field of semiconductors. The manufacturing method comprise providing a semiconductor substrate, and forming a hard mask layer defining the pattern of a shallow trench isolation structure on the surface of the semiconductor substrate; forming a shallow trench isolation structure in the semiconductor substrate with the surface of the shallow trench isolation structure being lower than that of the hard mask layer and higher than that of the semiconductor substrate; forming an advanced material layer on the surface of the shallow trench isolation structure through deposition; removing the hard mask layer; and removing the advanced material layer. According to the invention, by forming the advanced material layer on the shallow trench isolation structure, the surface of the shallow trench isolation structure can be effectively prevented from being etched and damaged during the wet method etching removal process of the hard mask layer, furthermore the STI effective field height fluctuation is small, and therefore the performance and the yield rate of the device are increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] In the semiconductor manufacturing process, the performance of the formed shallow trench isolation (STI) structure is critical to the performance and yield of the final formed semiconductor device. [0003] The manufacturing method of existing shallow trench isolation structure comprises the following main steps: as Figures 1A-1B As shown, at first, a buffer layer 101 and a hard mask layer (SiN) 102 are formed on a semiconductor substrate 100, the buffer layer and the hard mask layer are patterned, the semiconductor substrate is etched to form an opening of a shallow trench isolation structure, and then Deposit shallow trench isolation material 103 to fill the opening, perform CMP to stop on the hard mask layer 102, etch back part of the shallow trench isolation material 103, and then remove ...

AI Technical Summary

Problems solved by technology

[0004] When the size of CMOS devices is reduced to 28nm node and below, in the manufacturing process of shallow trench isolation structures, after the hard mask layer SiN in the active region is removed, the EFH control of shallow trench isolation structures (STI) becomes more and more difficult. more and more difficult

Usually using hot H 3 PO 4 to remove the hard mask layer SiN, but the H 3 PO 4 When contacting the STI, the material filled in the shallow trench isolation structure will be etched, and the new H 3 PO 4 and the old H 3 PO 4 The etching amount of the shallow trench isolation structure is not the same (such as Figure 1B As shown in the upper and lower figures), the effective field height of STI fluctuates greatly, which in turn affects the thickness uniformity of polysilicon deposition during gate fabrication, resulting in the loss of yield and performance of the final device

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