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High-speed parallel low-density parity-check decoder with multi-core scheduling and its decoding method

A low-density parity and decoder technology, applied in the field of high-speed parallel low-density parity-check decoder and its decoding, can solve the problem of insufficient utilization of hardware resources

Active Publication Date: 2020-07-07
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] The purpose of the present invention is to solve the problem of insufficient utilization of hardware resources in traditional high-speed LDPC decoders with limited resources, and propose a new type of multi-core scheduling high-speed parallel low-density parity check (LDPC) decoder and its decoder. The decoding method can control the decoding core to perform a non-fixed number of iterations through the new multi-core scheduling module, thereby effectively improving the decoding efficiency and making full use of hardware resources

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  • High-speed parallel low-density parity-check decoder with multi-core scheduling and its decoding method
  • High-speed parallel low-density parity-check decoder with multi-core scheduling and its decoding method
  • High-speed parallel low-density parity-check decoder with multi-core scheduling and its decoding method

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Embodiment Construction

[0027] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0028] A kind of high-speed LDPC decoder of multi-core scheduling proposed by the present invention, such as figure 2 As shown, it includes sequentially connected data cache modules, multi-core scheduling modules, and LDPC parallel decoding cores composed of multiple decoding cores, which can be implemented with an FPGA chip the same as traditional LDPC decoders; this multi-core scheduling high-speed The difference between the LDPC decoder and the traditional decoder is:

[0029] 1) The data buffer module is composed of FIFO inside the FPGA. This FIFO has a deeper storage depth than the FIFO in the traditional LDPC decoder data buffer module, so that more codeword sequence information can be cached to ensure that the next codeword arrives. , can have enough buffer space, after a decoding core completes the decoding of the previous code word, assign the new ...

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Abstract

The invention relates to a high speed parallel low density parity check decoder and a decoding method thereof for multi-core scheduling, and belongs to the technical field of wireless communications. The decoder comprises a data cache module, a multi-core scheduling module and an LDPC (Low Density Parity Check) parallel decoding kernel composed of a plurality of decoding kernels, which are orderly connected with each other. The method comprises the following steps: for a word stream to be decoded, assigning a codeword to be decoded with the length of a single codeword to a decoding kernel in an idle state by the multi-core scheduling module according to the working condition of a back-end parallel decoding kernel; checking whether the decoding kernel has finished decoding by the multi-core scheduling module; if decoding result verification is satisfied, then outputting a decoding result to the multi-core scheduling module; and after the decoding is finished, outputting the decoding result of each decoding kernel to the data cache module uniformly by the multi-core scheduling module according to a codeword allocation order and in the same order, and outputting decoding data by the data cache module. The high speed parallel low density parity check decoder and the decoding method thereof for the multi-core scheduling provided by the invention effectively improve the operation efficiency and the decoding speed of the decoder by adding the new multi-core scheduling module.

Description

technical field [0001] The invention belongs to the technical field of wireless communication, and relates to a multi-core scheduling high-speed parallel low-density parity-check decoder and a decoding method thereof. Background technique [0002] With the rapid development of the economy, both civilian and military fields have put forward higher requirements for high resolution and high precision, and a mature and stable high resolution (high resolution) system is very important for national military security and many civilian applications. Fields are important supports. In the high-resolution field, the United States first developed a high-resolution observation satellite, making this technology a world leader, and due to limited space resources and the extraordinary importance of data in the era of big data, the leading high-resolution technology The country is unwilling to share resources, so it is urgent to carry out high-scoring research and development independently....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
CPCH03M13/1128
Inventor 殷柳国张远东葛广君
Owner TSINGHUA UNIV
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