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Semiconductor device having chip ID generation circuit and multi-chip package

A technology for multi-chip packaging and circuit generation. It is used in instruments, static memory, read-only memory, etc., and can solve problems such as increasing manufacturing costs and reducing semiconductor manufacturing yields.

Active Publication Date: 2017-07-21
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, memory chips included in the multi-chip package but without any defect are also discarded, thereby reducing semiconductor manufacturing yield and increasing manufacturing cost

Method used

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  • Semiconductor device having chip ID generation circuit and multi-chip package
  • Semiconductor device having chip ID generation circuit and multi-chip package
  • Semiconductor device having chip ID generation circuit and multi-chip package

Examples

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Embodiment Construction

[0018] Hereinafter, example exemplary embodiments will be described in detail with reference to the accompanying drawings. Because the exemplary embodiments may have various modified embodiments, some embodiments are illustrated in the drawings and described in the detailed description of the exemplary embodiments. However, this does not limit the inventive concept to specific exemplary embodiments, and it should be understood that the inventive concept covers all modifications, equivalents and substitutions within the idea and technical scope of the inventive concept. Like reference numbers refer to like elements throughout. In the drawings, the size and size of each structure is exaggerated, reduced, or schematically illustrated for convenience and clarity of description.

[0019] Among semiconductor devices, a high-capacity dynamic random access memory (DRAM) may be implemented in a multi-chip package including a plurality of memory dies or memory layers. For example, eac...

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Abstract

Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2015-0151101 filed in the Korean Intellectual Property Office on Oct. 29, 2015, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0003] Exemplary embodiments of the subject matter described herein relate to a semiconductor device, and more particularly, to a multi-chip package including a chip ID generation circuit that flexibly reassigns chip IDs of memory chips of a stacked memory device. Background technique [0004] Semiconductor devices are designed and manufactured for high performance, high density, low cost and small size. Multi-chip packaging technology is being developed, in which multiple chips are integrated into a single package. Multi-chip packaging technology may be used so that a processor and a memory chip, a logic chip and a memory chip, or a memory chip are integrated into a single pa...

Claims

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Application Information

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IPC IPC(8): G11C5/02
CPCG11C5/02G11C29/88G11C8/12G11C2029/4402G11C17/16G11C17/18G11C29/1201G06F11/16
Inventor 卢亮均柳济民金玄基郑伦在
Owner SAMSUNG ELECTRONICS CO LTD