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An optimization method for on-chip area management of reconfigurable devices

An optimization method and device technology, applied in the direction of instruments, electrical digital data processing, multi-programming devices, etc., can solve problems such as complex vertex list management, achieve fast and efficient on-chip area management, easy implementation, and fast and efficient selection of candidate positions Effect

Active Publication Date: 2020-08-11
WUHAN UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This method can manage the processing area with higher efficiency, but the management of the vertex list is very complicated due to the insertion and deletion of tasks

Method used

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  • An optimization method for on-chip area management of reconfigurable devices
  • An optimization method for on-chip area management of reconfigurable devices
  • An optimization method for on-chip area management of reconfigurable devices

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Embodiment Construction

[0038] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, which are not intended to limit the protection scope thereof.

[0039] A method for optimizing the on-chip area management of a reconfigurable device, the specific implementation process of which is as follows.

[0040] The first step, modeling of reconfigurable devices

[0041] The reconfigurable device is composed of multiple configurable logic blocks (Configurable Logic Block, CLB), and the reconfigurable device is modeled as a two-dimensional array C(X,Y), where X and Y are the arrays composed of CLBs width and height. The two-bit array C(X,Y) formed by the reconfigurable device modeling is called a reconfigurable matrix, and each unit in the reconfigurable matrix corresponds to an array member in the two-bit array C(X,Y) , that is, each unit in the reconfigurable matrix is ​​a CLB on the reconfigurable device. The first unit in the upper ...

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Abstract

The invention provides a reconfigurable device on-chip area management optimization method. The method is characterized in that four kinds of vertexes of a reconfigurable device are used as candidate positions; a proper clear area is found via one kind of the vertexes as an area distribution object; areas used by finished tasks are combined via the vertexes. The method achieves rapid and efficient on-chip area management and candidate position selection and enables effective management of reconfigurable device on-chip areas.

Description

technical field [0001] The invention relates to the field of reconfigurable technology, in particular to a method for managing and optimizing the on-chip area of ​​a reconfigurable device. Background technique [0002] Reconfigurable computing is regarded as an effective solution that can combine the high flexibility of traditional processors with the high processing efficiency of ASIC (Application Specific Integrated Circuit). Due to the good adaptability of the reconfigurable architecture, the processing speed can be accelerated through different granularities of parallelism for different applications. Among reconfigurable devices, FPGA (Field-Programmable Gate Array) is the most widely used reconfigurable device. Dynamically rechargeable and configurable FPGA is an important basis for realizing hardware-level multitasking. The processing area of ​​this type of FPGA is usually divided into different sub-blocks, configurable logic blocks (Configurable Logic Block, CLB). ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
CPCG06F9/5044
Inventor 胡威张瑜沈欢刘小明张凯刘俊贺娟娟王磊马添奥马荣萱
Owner WUHAN UNIV OF SCI & TECH