FPGA circuit and configuration file processing method thereof

A technology of configuration file and processing method, applied in the direction of response error generation, redundant code error detection, etc., can solve problems such as internal register errors

Active Publication Date: 2017-08-04
CAPITAL MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Aerospace-grade large-scale FPGAs are all based on SRAM type. When SRAM type FPGAs are used in occasions with high reliability requirements, error detection must be performed by reading back the configuration file, but its internal registers are easily affected by the single instance effect. mistake

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  • FPGA circuit and configuration file processing method thereof
  • FPGA circuit and configuration file processing method thereof
  • FPGA circuit and configuration file processing method thereof

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Embodiment Construction

[0013] The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0014] In the embodiment of the present invention, a configuration structure of ECC code is added to the FPGA configuration file, and the FPGA device performs readback, inspection and error correction of the FPGA configuration file based on the ECC code during operation. By using this architecture, the ability of FPGA to support single event flipping can be greatly enhanced.

[0015] figure 1 Describes a configuration file structure with ECC checksums. The FPGA configuration file takes the length of the configuration chain as the unit and adds the ECC check code. exist figure 1 Among them, each group data Data corresponds to each configuration memory chain, and each configuration memory chain has an ECC coded check digit. The configuration file for configuring the entire FPGA chip includes several sets of data and ...

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Abstract

The invention discloses an FPGA circuit and a configuration file processing method. In one embodiment, the FPGA circuit comprises a configuration memorizer, a hardware ECC decoder and a single event upset controller. The configuration memorizer is used for storing FPGA configuration files, and the configuration files comprise configuration data and ECC codes; the hardware ECC decoder corrects and detects the configuration data through the ECC codes; the single event upset controller is used for reading back the configuration files and checking and correcting the read-back configuration files through the hardware ECC decoder. By means of the circuit, the capacity of an FPGA of supporting single event upset is greatly enhanced, therefore, the FPGA can be applied to the fields of astronavigation or aviation or other fields sensitive to errors of equipment, and therefore wide and great significance is achieved.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to an FPGA circuit and its configuration file processing method. Background technique [0002] With the advancement of technology, the requirements for on-board signal processing capabilities are getting higher and higher, and FPGAs are increasingly used in the aerospace field, becoming a key component of on-board signal processing and control. At present, judging from the use of FPGAs in spaceborne models, single event effects have become the main factor affecting the availability and reliability of large-scale FPGAs. [0003] Aerospace-grade large-scale FPGAs are all based on SRAM type. When SRAM type FPGAs are used in occasions with high reliability requirements, error detection must be performed by reading back the configuration file, but its internal registers are easily affected by the single instance effect. mistake. Therefore, it is very important and urgent to conduct anti-single ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10
CPCG06F11/10
Inventor 何轲秦波王宏宇
Owner CAPITAL MICROELECTRONICS
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