PCIE-based FPGA updating system and method

A base address and device technology, which is applied in the field of PCIE-based FPGA update system, can solve the problems of unsatisfactory large-scale update and slow loading speed of FPGA update speed, so as to improve FPGA loading speed, save labor cost and improve work efficiency Effect

Inactive Publication Date: 2017-08-11
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is used to solve the problem of slow FPGA update speed or loading speed in the prior art, and cannot satisfy large-scale updates

Method used

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  • PCIE-based FPGA updating system and method
  • PCIE-based FPGA updating system and method
  • PCIE-based FPGA updating system and method

Examples

Experimental program
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Embodiment Construction

[0034] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0035] Such as figure 1 As shown, it is a schematic diagram of the equipment structure of the PCIE-based FPGA update system in Embodiment 1 of the present invention. The update system includes a CPU device 101, an erasable programmable logic (Erasable Programmable LogicDevice, EPLD) device 102, a non-volatile Flash memory (NOR Flash) storage unit 103, Field Programmable Gate Array (Field Programmable Gate Array, FPGA) device 104, JTAG (Joint Test Action Group) download interface 105, wherein CPU device 101 is connected with FPGA device 104 through PCIE interface, FPGA device 104 is connected with EPLD device 102 through internal bus interface and FPGA configuration signal line, and EPLD device 102 is connected with NOR Flash storage unit 103 through FLASH read and write signal line, and JTAG download interface 105 is the download interface that FPGA de...

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Abstract

The invention relates to a PCIE-based FPGA updating system and method. The system comprises a CPU device, an EPLD device, an NOR Flash storage unit, an FPGA device and a JTAG downloading interface; the updating method comprises writing operation, reading operation and configuration operation; the CPU device adopts PCIE for performing communication, so that the data transmission speed is extremely high; and the FPGA configuration is finished by the EPLD device and is no longer started by depending on a CPU, so that the FPGA loading speed can be effectively increased. The method supports remote configuration; and when the scale is relatively large or a device deployment distance is relatively long, the working efficiency can be effectively improved and the labor cost can be reduced.

Description

technical field [0001] The invention relates to the technical field of electronic communication, in particular to a PCIE-based FPGA update system and update method. Background technique [0002] Currently. With the increase of digital communication protocols, Field Programmable Gate Array (Field Programmable GateArray, FPGA) is more and more widely used. Due to its characteristics of easy programming and fast upgrade architecture, it has been widely used in electronic equipment. [0003] Such as figure 1 As shown, the system is a reconfigurable computing system, using reusable resources of the system (such as: CPU, FPGA, Erasable Programmable Logic Device, EPLD) and other reconfigurable logic devices, according to The application needs to reconstruct a new computing platform to achieve high performance close to that of dedicated hardware design. Among them, CPU is the core processing platform, FPGA is the auxiliary processing platform, and EPLD mainly completes power-on co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445G06F5/06
CPCG06F5/065G06F8/654G06F2213/0024
Inventor 李韬熊智挺吕高锋孙志刚崔向东赵国鸿毛席龙杨惠全巍
Owner NAT UNIV OF DEFENSE TECH
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