PCIE-based FPGA updating system and method

Abstract

The invention relates to a PCIE-based FPGA updating system and method. The system comprises a CPU device, an EPLD device, an NOR Flash storage unit, an FPGA device and a JTAG downloading interface; the updating method comprises writing operation, reading operation and configuration operation; the CPU device adopts PCIE for performing communication, so that the data transmission speed is extremely high; and the FPGA configuration is finished by the EPLD device and is no longer started by depending on a CPU, so that the FPGA loading speed can be effectively increased. The method supports remote configuration; and when the scale is relatively large or a device deployment distance is relatively long, the working efficiency can be effectively improved and the labor cost can be reduced.

Description

technical field [0001] The invention relates to the technical field of electronic communication, in particular to a PCIE-based FPGA update system and update method. Background technique [0002] Currently. With the increase of digital communication protocols, Field Programmable Gate Array (Field Programmable GateArray, FPGA) is more and more widely used. Due to its characteristics of easy programming and fast upgrade architecture, it has been widely used in electronic equipment. [0003] Such as figure 1 As shown, the system is a reconfigurable computing system, using reusable resources of the system (such as: CPU, FPGA, Erasable Programmable Logic Device, EPLD) and other reconfigurable logic devices, according to The application needs to reconstruct a new computing platform to achieve high performance close to that of dedicated hardware design. Among them, CPU is the core processing platform, FPGA is the auxiliary processing platform, and EPLD mainly completes power-on co...

AI Technical Summary

Problems solved by technology

It is used to solve the problem of slow FPGA update speed or loading speed in the prior art, and cannot satisfy large-scale updates

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