Semiconductor device and method of forming the same

Abstract

Embodiments of the present invention provide a method of forming a semiconductor device including forming a fin extending from a substrate. The fin has a source / drain (S / D) region and a channel region. The fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition. The method also includes removing the first semiconductor layer from the S / D region of the fin such that a first portion of the second semiconductor layer in the S / D region is suspended in the spacer. The method also includes epitaxially growing a third semiconductor layer in the S / D region, the third semiconductor layer surrounding the first portion of the second semiconductor layer. The embodiment of the invention also provides a semiconductor device.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and more particularly to semiconductor devices and methods of forming the same. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple IC generations, each with smaller and more complex circuits than the previous generation. During IC development, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component (or line) that can be made using a fabrication process) has decreased. This scale-down process also typically has the benefit of increasing throughput efficiency and reducing associated costs. This scaling down has also increased the complexity of handling and manufacturing ICs, and in order to realize these advances, similar developments in IC handling a...

AI Technical Summary

Problems solved by technology

HGAA transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, however, fabrication of HGAA transistors can be challenging

For example, existing methods for source and drain (S / D) formation of HGAA transistors cannot meet the needs in all aspects, especially when the device pitch is small, such as 40 nanometers (nm) or less

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