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Method of component partitions on system on chip and device thereof

A component and chip technology, applied in the field of component division of system-on-chip, can solve problems such as high production costs

Inactive Publication Date: 2017-08-18
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unidentified handling of different metal layers can lead to higher production costs

Method used

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  • Method of component partitions on system on chip and device thereof
  • Method of component partitions on system on chip and device thereof
  • Method of component partitions on system on chip and device thereof

Examples

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Embodiment Construction

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which the first component and the second component may be formed in direct contact. An embodiment in which an additional part is formed so that the first part and the second part may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the sake of simplicity and clarity and does not in itself indicate a relations...

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Abstract

A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and more specifically relate to a method for dividing components of a system on a chip and devices thereof. Background technique [0002] Improvements in integration come from ever-decreasing minimum component sizes, which allow more components to fit into a given area. In an attempt to increase circuit density, research has been conducted on three-dimensional (3D) integrated circuits (ICs). In a typical formation process for a 3DIC, two dies are bonded together and an electrical connection is made between each die and a contact pad on the substrate. Interposer stacking is part of 3D IC technology where through silicon via (TSV) embedded interposers are connected to the device silicon with microbumps. 3D IC manufacturing process flow can be divided into two types. In a chip-on-substrate (CoCos) process flow, a silicon interposer chip is first attached to a package substrate,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L25/065H01L23/48
CPCH01L21/50H01L23/481H01L25/065H01L23/147H01L23/522H01L23/49827H01L25/50H01L25/04G06F30/392G06F30/394G06F2115/02H01L21/486H01L21/76883H01L21/76898H01L23/49838H01L23/5226H01L23/528H01L25/0657H01L2225/06541H01L2225/06548
Inventor 侯永清桑迪·库马·戈埃尔李云汉
Owner TAIWAN SEMICON MFG CO LTD
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