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Method for parallel processing of TDS-FDM timing synchronization

A technology of timing synchronization and parallel processing, applied in the direction of multi-frequency code system, etc., can solve the problems of low complexity and high bit error performance

Inactive Publication Date: 2017-08-29
HANGZHOU DIANZI UNIV
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Problems solved by technology

[0006] The purpose of the present invention is to provide a symbol timing fast synchronization method with faster synchronization speed and better performance for the existing symbol timing synchronization method that cannot have low complexity, high bit error performance and fast synchronization at the same time. Parallel processing of TDS-OFDM timing synchronization method, so as to be widely used in digital communication fields such as terrestrial wireless emergency communication, satellite and power line communication suitable for low signal-to-noise ratio transmission

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  • Method for parallel processing of TDS-FDM timing synchronization
  • Method for parallel processing of TDS-FDM timing synchronization
  • Method for parallel processing of TDS-FDM timing synchronization

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Embodiment Construction

[0095] The present invention will be described in further detail below through specific embodiments and in conjunction with the accompanying drawings.

[0096] The parallel processing TDS-OFDM timing synchronization method provided by the present invention can be applied to high-speed digital communication fields such as wireless and power lines, and is not limited to the fields described in detail in the following embodiments. In the following, a typical parallel processing TDS-OFDM timing synchronization method is selected to describe the specific implementation manner of the present invention in detail.

[0097] The present invention is realized through the following main steps successively: the received analog signal becomes a digital signal by analog / digital conversion after being down-converted; Filling method of guard interval in cross frequency division multiplexing modulation system: China, CN1334655A[P].2002-02-06.") Fill guard interval by PN sequence to form TDS-OFD...

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Abstract

The present invention discloses a method for parallel processing of TDS-FDM timing synchronization. The method comprises: a parallel TDS-OFDM timing synchronization interpolation method, a parallel TDS-OFDM timing error detection method and a parallel TDS-OFDM interpolation control method. The method for parallel processing of TDS-FDM timing synchronization performs timing synchronization interpolation to detect timing errors, generate resampling signals and update parameters such as step values and the like to realize one more interpolation, an interpolation method is employed to perform resampling time clock phase regulation, extract optimal sampling point amplitude and polarity changing information of adjacent code elements and determine whether the transition points of the adjacent code elements are zero or not to form a timing synchronization algorithm with low complexity, high in error code performance and rapid synchronization.

Description

technical field [0001] The invention belongs to the technical field of digital communication, in particular to a method for parallel processing TDS-OFDM timing synchronization. Background technique [0002] The most important component in the all-digital receiver is the timing synchronization loop, which has an important impact on system performance. Timing synchronous loop structure is generally divided into two categories: feedforward structure and feedback structure. The timing error detectors in the feedforward structure and the feedback structure can be further divided into: data-assisted and non-data-assisted. Among them, the Gardner timing synchronization loop based on the feedback structure does not need auxiliary data, and each symbol only needs 2 samples, and is independent of the carrier phase, so the implementation complexity is low, and it is generally used in practice. However, the performance analysis of the feedback timing loop is relatively complicated. At...

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Application Information

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IPC IPC(8): H04L27/26
Inventor 姜斌包建荣李阳光唐向宏刘超王天枢
Owner HANGZHOU DIANZI UNIV
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