Multi-core processor deterministic repetition-oriented optimized segmental memory competition recording system and method

A multi-core processor and recording system technology, applied in the direction of multi-channel program device, program synchronization, hardware monitoring, etc., can solve the problems of conflicting dependencies, unable to find out records, record redundancy, etc., to optimize memory contention logs, The effect of reducing the number of times

Inactive Publication Date: 2017-09-22
HARBIN INST OF TECH AT WEIHAI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Among them, the current segmented memory contention recording method still has record redundancy, and the judgment method of the derivable reduction algorithm still has deficiencies. It is impossible to find and record some non-derivable conflict dependencies, and the non-derivable conflicts There is also a method for further optimization of dependency records, which can further reduce the number of records, reduce hardware resource consumption, and improve the efficiency of deterministic replay

Method used

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  • Multi-core processor deterministic repetition-oriented optimized segmental memory competition recording system and method
  • Multi-core processor deterministic repetition-oriented optimized segmental memory competition recording system and method
  • Multi-core processor deterministic repetition-oriented optimized segmental memory competition recording system and method

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specific Embodiment approach 1

[0033] Specific implementation mode one: combine figure 1 with figure 2 To illustrate, the optimized segmented memory contention recording system for multi-core processor deterministic replay described in this embodiment includes n processor cores and shared data buffer memory (L2Cache), wherein the n processors Each processor core includes a memory contention recording module (DRstate), a private data buffer memory (L1 Cache), a private instruction buffer memory (Instructions L1 Cache), a coherent protocol controller (Protocol controller), and a data transmission channel; its characteristics In that: the memory contention recording module (DRstate) includes an instruction counter (IIC), a segment counter (SC), a control logic module (CL) and a segment number register (SN);

[0034] Instruction counter (IIC), used to record the number of instructions;

[0035] Segment counter (SC), used to record the segment number of the processor core;

[0036] Control logic module (CL),...

specific Embodiment approach 2

[0043] Specific embodiment two: this embodiment is based on the memory recording method of the multi-core processor deterministic replay-oriented optimized segmentation memory contention recording system described in specific embodiment one, and the working process of the described control logic module includes The following steps:

[0044] When the submitted instruction is a memory operation instruction, update the value of the instruction counter IC, and set the segment number of the memory block corresponding to the memory operation;

[0045] When a requester consistency request is received, a step of detecting whether memory competition occurs through a buffer memory (Cache) consistency protocol controller;

[0046] When the cache memory (Cache) coherence protocol controller detects the memory competition, the step of judging whether the memory competition needs to be recorded is determined by using an optimization segmentation method;

[0047] When the memory competition...

specific Embodiment approach 3

[0050] Specific implementation mode three: combination image 3 , this embodiment is a further limitation of the memory contention recording method oriented to multi-core processor deterministic replay described in the second specific embodiment, when the cache memory (Cache) coherence protocol controller detects memory contention, use The steps of optimizing the segmentation method to determine whether the memory competition needs to be recorded are as follows:

[0051] When a new memory competition is detected, compare it with the current occurrence sequence of each pair of conflicts that have been recorded. If there is a pair of recorded conflicts whose segment number is greater than the first occurrence of the conflict, the later occurrence If the segment number is smaller than the party after the conflict, it means that the current sequence of occurrence of the conflict can be deduced and will not be recorded. Otherwise, it is determined that the memory competition needs ...

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Abstract

The invention discloses a multi-core processor deterministic repetition-oriented optimized segmental memory competition recording system and method, and relates to a memory competition recording system. In order to solve the problem of missing recording caused by redundancy and judgment mode deficiency of an existing segmental memory competition recording method, a segment number register is arranged, so that optimized recording of memory competition of a multi-core processor is realized; according to the recording method, when a memory competition conflict is detected, current competition records are effectively compared with previous competition records, whether the competition records can be reduced or not is judged, and whether manual access conflict setting can be performed by utilizing an adjacent homodromous competition relationship is judged, so that the effects of reducing a memory competition recording frequency, optimizing a memory competition log and reducing hardware resource consumption are achieved; and the method can be extended to more extensive application models of fault-tolerance processing, after-event security analysis and the like.

Description

technical field [0001] The invention relates to a memory contention recording system, in particular to a memory contention recording system and a method thereof for multi-core processor deterministic replay. Background technique [0002] With the rapid development of microelectronics technology, on-chip multi-core processors have become the mainstream computing platform and research hotspot. On-chip multi-core processors are usually shared-memory scalable systems based on directory-based buffer memory (Cache) coherence protocols, allowing multiple threads running on multiple processor cores to simultaneously access shared memory. Although the directory-based cache (Cache) coherence protocol can effectively prevent the inconsistency of shared memory, it has no control over the order of access between multiple threads, especially when data competition occurs, and each execution may get a different result. Results of the. The uncertainty of the multi-core processor execution ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/52G06F11/34
CPCG06F9/52G06F11/34
Inventor 姬壮伟季振洲陈彬
Owner HARBIN INST OF TECH AT WEIHAI
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