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Supercomputer using wafer scale integration

一种晶片、芯片的技术，应用在大规模并行超级计算机领域，能够解决电气连接数限制等问题

Active Publication Date: 2017-10-13
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The size of a single chip is limited by lithography size, output and chip packaging technology, and the number of electrical connections between chips is also limited by chip packaging technology

Method used

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  • Supercomputer using wafer scale integration
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  • Supercomputer using wafer scale integration

Examples

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Embodiment Construction

[0030] Exemplary embodiments of the invention described herein generally include supercomputers fabricated using wafer-level integration and methods of fabrication thereof. Therefore, while the embodiments of the present invention are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that there is no intention to limit the embodiments of the invention to the particular exemplary embodiments disclosed, but on the contrary, embodiments of the invention are to cover all modifications, equivalents, and alternatives falling within the scope of the invention.

[0031] Exemplary embodiments of the invention include a wafer whose surface is completely populated with many small processors that are electrically interconnected using upper-level chip wiring, a connectivity scheme known as wafer-level integration. Chip-to-chip in...

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PUM

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Abstract

A semiconductor structure includes a substrate with cooling layers, cooling channels, coolant inlets and outlets in fluid communication with the cooling channels, and a device layer on the cooling layers with one or more connection points and a device layer area. The device layer thermal coefficient of expansion is substantially equal to that of the cooling layers. A plurality of laminate substrates are disposed on, and electrically attached to, the device layer. The laminate substrate thermal coefficient of expansion differs from that of the device layer, each laminate substrate is smaller than the device layer portion to which it is attached, and each laminate substrate includes gaps between sides of adjacent laminate substrates. The laminate substrates are not electrically or mechanically connected to each other across the gaps therebetween and the laminate substrates are small enough to prevent warping of the device, interconnection and cooling layers due to thermal expansion.

Description

technical field [0001] Embodiments of the invention relate to massively parallel supercomputers made from multi-core processor chips. Background technique [0002] Contemporary supercomputers typically use tens of thousands of processors that are distributed over a network or placed close to each other as in a centralized computer cluster. More recently, supercomputers have started using multi-core processors, with the idea of ​​developing a supercomputer on a chip. The bisecting bandwidth between separate processor chips in a supercomputer is generally limited by the speed and number of electrical connections that can be provided between the processors. The available bandwidth between processors on the same chip is significantly higher than what is typically available between processors on different chips. The size of a single chip is limited by lithography size, output and chip packaging technology, and the number of electrical connections between chips is also limited b...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/70
CPCH01L2224/92242H01L24/94H01L24/97H01L25/50H01L2224/04026H01L2224/05644H01L2224/05655H01L2224/05666H01L2224/13109H01L2224/13116H01L2224/16227H01L2224/24137H01L2224/29116H01L2224/2919H01L2224/32225H01L2224/73204H01L2224/73253H01L2224/81805H01L2224/92125H01L2224/94H01L2224/97H01L2924/1431H01L2924/1434H01L2924/157H01L2924/15787H01L2924/15788H01L2224/05583G06F2200/201G06F1/20H01L23/367H01L23/473H01L2224/83H01L2924/0105H01L2224/81H01L2224/16225H01L2924/00G06F1/185H01L23/49816H01L23/49838
Inventor E.G.科尔根M.M.丹内奥J.尼克博克
Owner INT BUSINESS MASCH CORP
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