A device for performing vector logic operations

Abstract

The present disclosure provides a device and method for performing vector logic operations, which are used to cooperate with a set of instruction sets to execute vector logic operations. The device includes a storage unit, a register unit, and a vector logic operation unit, and the storage unit stores a vector , the address of vector storage is stored in the register unit, the vector logic operation unit obtains the vector address in the register unit according to the supporting instruction, and then obtains the corresponding vector in the storage unit according to the vector address, and then performs vector logic according to the obtained vector operation to get the result of the operation. The disclosure temporarily stores the vector data involved in the calculation in a high-speed temporary storage memory, so that data of different widths can be more flexibly and effectively supported during the vector logic operation process, and the execution performance of applications involving a large number of vector logic operations is improved.

Description

technical field [0001] The present disclosure relates to an apparatus and method for performing vector logic operations. Background technique [0002] Among the existing applications in the computer field, applications related to vector operations are very common. Taking the mainstream algorithm machine learning algorithm in the current hot application field of artificial intelligence as an example, almost all existing classic algorithms contain a large number of vector logic operations related to the present disclosure. Vector logic operations refer to the four operations of vector inter-and, intra-and, inter-or and intra-or, where, for two vectors a=[a1,a2,…,an] and b=[b1,b2,…,bn] , the inter-AND operation is defined as: [a1&b1,a2&b2,…,an&bn]; the inner-AND operation of a vector a is defined as: a1&a2&…&an; the inter-vector OR operation is defined as: [a1||b1,a2||b2,…,an ||bn]; the inner or definition of vector a is: a1||a2||…||an. [0003] In the prior art, a known sol...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present disclosure is to provide a device and method for performing vector logic operations to solve the problems existing in the prior art such as limited inter-chip communication, insufficient on-chip cache, and insufficient flexibility of supported vector lengths.

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