Enhanced electrostatic discharge (ESD) clamp

An electrostatic discharge and clamping technology, which is used in electric solid devices, circuits, emergency protection circuit devices for limiting overcurrent/overvoltage, etc., and can solve problems such as inability to protect on-voltage semiconductor devices

Pending Publication Date: 2017-11-03
INTERSIL INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, existing MOSFET-based clamps for ESD protection cannot protect any semiconduc

Method used

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  • Enhanced electrostatic discharge (ESD) clamp
  • Enhanced electrostatic discharge (ESD) clamp
  • Enhanced electrostatic discharge (ESD) clamp

Examples

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Embodiment Construction

[0012] The present embodiments will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of the embodiments to enable those skilled in the art to practice embodiments and alternatives that will be apparent to those skilled in the art. It is worth noting that the following figures and examples are not meant to limit the scope of embodiments of the present invention to a single embodiment, but other embodiments may be realized by exchanging some or all of the described or illustrated elements . Furthermore, where certain elements of the present embodiment can be partially or fully realized using known components, only those parts of these known components necessary for understanding the present embodiment will be described, and the description of other parts of these known components will be described. A detailed description will be omitted so as not to obscure the present embodiment. Embodiments described as implem...

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Abstract

An enhanced ESD clamp is provided with a resistor connected between the body terminal and the source terminal of a MOSFET device. In one exemplary embodiment, the MOSFET device is a grounded-gate NMOS (ggNMOS) transistor device with the resistor ('body resistor') connected externally to the MOSFET device. In another embodiment, the MOSFET device is a ggPMOS transistor device. In yet another embodiment, the body resistor is disposed within and connected internally to the MOSFET device. In any event, the resistance value of the body resistor determines the level to which the trigger voltage of the ESD clamp will be reduced when an ESD event occurs.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 327,719, filed April 26, 2016, and U.S. Provisional Patent Application Serial No. 62 / 469,894, filed March 10, 2017, the entire contents of which applications are incorporated by reference Incorporated into this article. technical field [0003] The present embodiments relate generally to electrostatic discharge (ESD) protection, and more particularly to enhanced ESD clamps for integrated circuits. Background technique [0004] Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are commonly used for electrostatic discharge (ESD) protection in CMOS integrated circuits to clamp any large ESD-induced voltage pulses to a low enough level to avoid damage to the integrated circuits involved. Semiconductor devices and / or metal interconnections in a circuit chip. However, existing MOSFET-based clamps for ESD protection cannot...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0277H01L27/0288H02H9/046
Inventor 阿布·T·卡比尔
Owner INTERSIL INC
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