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FPGA training and inquiry circuit achievement method based on perfect hash algorithm

A query circuit and hash algorithm technology, which is applied in computing, electrical digital data processing, special data processing applications, etc., can solve the problems of large scale and low efficiency of second-order hashing

Active Publication Date: 2017-11-07
HUAXIN SAIMU CHENGDU TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The object of the present invention is to provide a kind of FPGA training and query circuit implementation method based on the perfect hash algorithm, for solving the problem that adopting FPGA to realize second-order hash scale is large and inefficient in the prior art, FPGA among the present invention The module implements the use of a given static key value table to generate a perfect hash structure. For any given key value, a unique, non-conflicting index number preset by the user can be queried

Method used

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  • FPGA training and inquiry circuit achievement method based on perfect hash algorithm
  • FPGA training and inquiry circuit achievement method based on perfect hash algorithm
  • FPGA training and inquiry circuit achievement method based on perfect hash algorithm

Examples

Experimental program
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Effect test

Embodiment 1

[0096] combined with Figure 1-3 As shown, a FPGA training and query circuit implementation method based on the perfect hash algorithm comprises the following steps:

[0097] S1) input the static key value and the hash index value of the static key value into the static key value table;

[0098] S2) performing a first-order hash calculation on the static key value and an input true random number to obtain a first-order hash table, and the entries of the first-order hash table include:

[0099] Address / Index: In the stage of rearranging static key values, it indicates the base address of the generated key value rearrangement table for static key values; after the second-order hash training is completed, that is, after the conflict group in the first-order hash table is resolved, If vld=1, col=0, it indicates the serial number of the static key value; if vld=1, col=1, it indicates the base address of the serial number of the static key value stored in the second-order hash tabl...

Embodiment 2

[0112] On the basis of Example 1, in conjunction with the attached Figure 1-3 and Figure 6 As shown, the step S2) is specifically:

[0113] S2.1) Empty the first-order hash table, so that the initial state of the first-order hash table is all 0;

[0114] S2.2) Perform a first-order hash calculation on the first static key value in the static key-value table and an input true random number to obtain the address index value of the first-order hash table, and write the serial number of the static key value into The address / index in the entry corresponding to the address index value of the first-order hash table, writing the col_cnt and col_rec of the entry into "1", and writing the valid indication vld of the entry into "1";

[0115] S2.3) Read the next static key value, perform first-order hash calculation, obtain the address index value of the first-order hash table corresponding to the static key value, and read the valid indication vld of the entry corresponding to the addr...

Embodiment 3

[0119] On the basis of embodiment 2, in conjunction with the attached Figure 1-3 and Figure 6 As shown, the step S3) is specifically:

[0120] S3.1) Set the FPGA internal counter base_addr_cnt to 0, read the first static key value in the static key value table, and read the col in the entry of the address index value corresponding to the static key value from the first-order hash table , if col is equal to 0, the static key value does not conflict, and the next static key value is directly read; otherwise, write the address / index of the entry corresponding to the static key value in the first-order hash table into base_addr_cnt= 0 as the base address in the key value rearrangement table, update base_addr_cnt=base_addr_cnt+col_rec, and use 0+col_cnt-1 as the absolute address of the static key value in the rearrangement table, copy the static key value to the Absolute address, at the same time, the col_cnt of the entry of the address index value corresponding to the static k...

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Abstract

The invention discloses an FPGA training and inquiry circuit achievement method based on a perfect hash algorithm. The method comprises the following steps of creating a static key value table; conducting first-order hash calculation on static key values and a true random number, and mapping results to a first-order hash table; making the static key values which conflict with one another in the same slot position in the first-order hash table constitute a conflict group, and duplicating the conflict group into adjacent positions of a key value rearranging table; conducting second-order hash calculation on the conflict group to obtain a second-order hash table in which conflict group mapping address index values are mutually different, wherein when serial numbers of the static key values are inquired, the address index values of the static key values are searched in the first-order hash table and / or the second-order hash table, the serial numbers of the static key values are read, and the hash index numbers can be output through serial number query. By utilizing the strong assembly line calculation capability of an FPGA, the size of the mapping space of the conflict group in the second-order hash table is gradually widened through trials from being initially set larger than or equal to 2 of integer power of the least of the conflict number, which drastically saves the volume of the second-order hash table.

Description

technical field [0001] The invention relates to the field of large-scale static data query, in particular to the field of FPGA query circuit design, specifically, an FPGA training and query circuit implementation method based on a perfect hash algorithm. Background technique [0002] In the existing technology, the common query method is to use the hash algorithm to query the index value based on the key value. For static data structures, people usually use perfect hashing to solve the conflict problem, that is, a two-stage hash operation method: first perform the second First-level hashing, find out the key values ​​that collide with the same slot; for each set of key-value groups that conflict with the same slot, find a hash function using the global hash method, so that the hash values ​​​​of these key values ​​have no conflict. These key-values ​​with first-order conflicts resolved will form a second-order hash. Most of the existing perfect hashing methods are aimed at...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/30
CPCG06F16/2264
Inventor 邓俊杰
Owner HUAXIN SAIMU CHENGDU TECH CO LTD
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