Silicon carbide device packaging structure and manufacturing method based on three-layer dbc substrate

Abstract

The invention discloses a three-layer DBC substrate-based silicon carbide package structure and a manufacturing method thereof. The package structure comprises an upper structure, an intermediate structure, a lower structure, two layers of nanometer silver welding paste, a longitudinal silicon carbide power chip and a high-temperature resistant filler, wherein the upper structure, the intermediate structure and the lower structure are formed by a three-layer pattern DBC substrate, a chip electrode is led out without a lead by patterning of the DBC substrate and connection by the nanometer silver welding paste, the interconnection area is expanded, the connection distance is shorted, and the additional resistance and inductance are reduced; moreover, leading-out electrodes are arranged on different planes, and the insulation performance is not affected by the thickness of an intermediate layer due to the design of a DBC pattern; meanwhile, the intermediate layer of the package structure is used as a heat dissipation passage, heat of upper-layer DBC can be transferred to lower-layer DBC, the heat dissipation passages are added, and heat generated by the chip also can be dissipated by an upper surface and a lower surface under the condition that a heat dissipation plate is not additionally arranged; and compared with other package modes, the package structure is simple in structure, enough in raw material and high in maneuverability, and has relatively universal applicability.

Description

technical field [0001] The invention relates to the field of semiconductor power device packaging, in particular to a silicon carbide device packaging structure and manufacturing method based on a three-layer DBC substrate. Background technique [0002] With the continuous development of the electronics industry, the performance requirements of electronic devices are constantly increasing, and the improvement of device power and device power density has become an inevitable trend. With the continuous research of the third-generation semiconductor materials in the field of semiconductor devices, the ensuing convenience It is the packaging problem of power devices. For silicon carbide devices, due to the superiority of the silicon carbide material itself, it has the advantages of high breakdown electric field strength, good thermal stability and high carrier saturation drift speed. The corresponding devices have high temperature resistance, and their maximum operating temperat...

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Problems solved by technology

For the packaging of high-temperature devices, due to the limitation of packaging technology and the flexibility of packaging materials, most of them use wire bonding to realize the interconnection of electrodes and substrates, which not only increases the package size and additional resistance, but also reduces the reliability of the package. The development of power devices will also gradually pay attention to the heat dissipation of the package. The current heat dissipation in a single direction limits the further increase of the package temperature. Most modules now use a direct copper-clad substrate as the base, and realize interconnection through wire bonding and external terminals. Although the heat dissipation path is increased to a certain extent and the reliability is improved, the existence of leads will inevitably bring about large additional inductance and resistance, and the heat dissipation on one side also limits the further improvement of the heat dissipation capability of the package, and the large parasitic parameters And too high chip junction temperature will bring a series of reliability problems, so it is necessary to optimize the packaging structure and packaging method

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