34results about How to "Shorten the interconnection distance" patented technology

A multi-wafer stack structure and fabricating method thereof are disclosed. In the multi-wafer stack structure, the first interconnection layer is electrically connected to the second metal layer and the first metal layer via the first opening, the second interconnection layer is electrically connected to the first interconnection layer via the second openings, the third interconnection layer is electrically connected to the third metal layer via the third openings, and the second interconnection layer is in contact with the third interconnection layer, so that there is no need to reserve the wire pressure welding space between the wafers and a silicon substrate is eliminated, the overall device thickness of the multi-wafer stack package is reduced. Moreover, the design processing of the silicon substrate and a plurality of common pads on the silicon substrate is eliminated, thereby reducing the parasitic capacitance and power loss, and increasing the transmission speed.

A multi-wafer bonding structure and bonding method are disclosed. The multi-wafer bonding structure includes a first unit and a second unit, a metal layer of each wafer in the first unit electrically connected to an interconnection layer of the first unit, a first bonding layer in the first unit electrically connected to the interconnection layer of the first unit, a second bonding layer in the second unit electrically connected to a metal layer of the second unit, and the first bonding layer being in contact with the second bonding layer to achieve an electrical connection, thereby achieving the electrical connection among the interconnection layer of the first unit, the first bonding layer, the second bonding layer and the metal layer of each wafer.

Integrated circuit fabrication techniques are provided which allow non-horizontal / non-vertical wires to traverse the entire chip surface, rather than just the comers as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

The invention discloses a MOSFET packaging structure and a manufacturing method thereof. The packaging structure includes a silicon substrate and a MOSFET chip. The front side of the MOSFET chip includes a source conductive pad and a gate conductive pad, and the back side includes a drain region and a metal layer. There is a sinking groove on the surface of the substrate, and the bottom of the sinking groove is laid with a conductive layer extending to the surface of the substrate as a drain conductive pad. The back of the MOSFET chip is mounted on the bottom of the sinking groove, and the metal layer and the sinking groove The conductive layer at the bottom is connected by metal bonding, the conductors interconnected with the outside are formed on the source conductive pad, the gate conductive pad and the drain conductive pad, and the part other than the conductor on the front side of the silicon substrate is encapsulated by the protective layer. The present invention guides the drain current on the back of the MOSFET with a vertical structure to the front of the MOSFET, realizes that the source, gate, and drain are electrically on the same side for wafer-level packaging, and the large-area conductive layer ensures a good chip Heat dissipation effect; avoiding the TSV process through silicon vias, simplifying the process steps and reducing the packaging cost.

The invention relates to a groove-interconnected wafer level metal-oxide-semiconductor field effect transistor (MOSFET) encapsulation structure and an implementation method. The structure comprises a chip body (1-1); a chip source electrode (2-1) and a chip gate electrode (2-2) are arranged on the front surface of the chip body; chip surface protection layers (3) are arranged on the front surfaces of the chip source electrode and the chip gate electrode of the chip body; chip grooves (1-2) pass through the front surface and the back surface of the chip body; circuit layers (4) are arranged onthe surface of the chip source electrode, the surface of the chip gate electrode and the surfaces of the chip surface protection layers (3) and in the chip grooves (1-2); a circuit surface protectionlayer (5) is arranged on the surface of the circuit layer; welded balls (6) are arranged on the surfaces of the circuit layers (4) on the front surface of the chip body (1-1); a back surface metal layer (7) is arranged on the back surface (1-3) of the chip body (1-1); and the back surface metal layer (7) is interconnected with the circuit layers (4). The encapsulation structure with high performance, and a process method which is used for implementing the structure and has high production efficiency and is low in encapsulation cost are provided.

The invention provides a photoelectric monolithic integrated system based on a multi-material system, the system includes an indium phosphide-silicon laser, a silicon passive photonic device, a silicon nitride passive photonic device, and a silicon nitride-lithium niobate electro-optic modulator The germanium-silicon detector and the electronic circuit are integrated on the same substrate, which is used to reduce the size of the optoelectronic system, reduce the electrical and optical interconnection distance, thereby greatly reducing the adverse effects of parasitic parameters on the integrated system; avoiding the optical path The packaging between the module and the circuit module reduces the packaging cost. Take advantage of the excellent electro-optical performance of lithium niobate material, low loss, low polarization sensitivity, high process tolerance and high refractive index of silicon nitride material to realize a monolithic optoelectronic integrated system with excellent performance.

A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.

The invention discloses an optical transmitter, which is applied in a photoelectric interconnection interface system, which includes: an electric chip and an optical chip connected to each other; the electric chip includes: a driver module and a matching module; Chip transmission; the optical chip is used to modulate the optical signal according to the driving signal to obtain a modulated signal and output it; the matching module is used to perform impedance matching on the driving signal output by the optical chip. The invention has the advantages of unrestricted device selection of the light emitter and high impedance matching precision.

The invention relates to a rear through-hole interconnected wafer level MOSFET (metal oxide semiconductor field effect transistor) packaging structure and an implementation method. A chip source electrode (2-1) and a chip gate electrode (2-2) are arranged on the front surface of a chip body (1-1); chip surface protecting layers (3) are arranged on the front surfaces of the chip body, the chip source electrode and the chip gate electrode; front surface circuit layers (4) are arranged on the surfaces of the chip body, the chip source electrode, the chip gate electrode and the chip surface protecting layers; circuit surface protecting layers (5) are arranged on the surfaces of the front surface circuit layers and the chip surface protecting layers; solder balls (7) are arranged on the surfaces of the front surface circuit layers; a chip through hole (1-2) is arranged by penetrating the front surface and the back surface of the chip body; and a circuit layer (6) is arranged on the back surface of the chip body, the circuit layer (6) is filled in the chip through hole, and the circuit layer filled in the chip through hole is in direct contact with the side wall of the chip through holeand interconnected with the front surface circuit layers. According to the invention, the packaging structure has high performance; and the process method which is used for implementing the structureand has the advantages of high production efficiency and low packaging cost.

The invention relates to a ferroelectric phase transition hybrid memory unit, memory and operation method. The ferroelectric phase change hybrid storage unit includes: a lower electrode, a functional layer and an upper electrode arranged in sequence; the lower electrode is a low work function electrode, and the upper electrode is a high work function electrode; the functional layer is a ferroelectric phase change material. By adopting the above structure, the ferroelectric phase-change hybrid storage unit can selectively work in the ferroelectric storage state or the phase-change storage state.