Rear through-hole interconnected wafer level MOSFET (metal oxide semiconductor field effect transistor) packaging structure and implementation method

Abstract

The invention relates to a rear through-hole interconnected wafer level MOSFET (metal oxide semiconductor field effect transistor) packaging structure and an implementation method. A chip source electrode (2-1) and a chip gate electrode (2-2) are arranged on the front surface of a chip body (1-1); chip surface protecting layers (3) are arranged on the front surfaces of the chip body, the chip source electrode and the chip gate electrode; front surface circuit layers (4) are arranged on the surfaces of the chip body, the chip source electrode, the chip gate electrode and the chip surface protecting layers; circuit surface protecting layers (5) are arranged on the surfaces of the front surface circuit layers and the chip surface protecting layers; solder balls (7) are arranged on the surfaces of the front surface circuit layers; a chip through hole (1-2) is arranged by penetrating the front surface and the back surface of the chip body; and a circuit layer (6) is arranged on the back surface of the chip body, the circuit layer (6) is filled in the chip through hole, and the circuit layer filled in the chip through hole is in direct contact with the side wall of the chip through hole and interconnected with the front surface circuit layers. According to the invention, the packaging structure has high performance; and the process method which is used for implementing the structure and has the advantages of high production efficiency and low packaging cost.

Description

technical field [0001] The invention relates to a wafer level chip size packaging structure and a realization method. It belongs to the technical field of semiconductor packaging. Background technique [0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a field effect transistor that uses electric field effects to control semiconductors. MOSFETs have received increasing attention in recent years due to their characteristic of enabling low power consumption voltage control. The performance of MOSFET, especially the current carrying capacity, largely depends on the heat dissipation performance, and the heat dissipation performance mainly depends on the package form. However, traditional MOSFET packages are mainly in the form of TO, SOT, SOP, QFN, QFP, etc. This type of package wraps the chip in a plastic package, which cannot conduct or dissipate the heat generated by the chip in time, which restricts the performance improvement of the MSOFET. . Moreover,...

AI Technical Summary

Problems solved by technology

However, traditional MOSFET packages are mainly in the form of TO, SOT, SOP, QFN, QFP, etc. This type of package wraps the chip in a plastic package, which cannot conduct or dissipate the heat generated by the chip in time, which restricts the performance improvement of the MSOFET.

Moreover, the plastic packaging itself increases the size of the device, which does not meet the requirements of the development of semiconductors in the direction of light, thin, short, and small

As far as the packaging process is concerned, this type of packaging is based on a single chip, which has the problems of low production efficiency and high packaging cost

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